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* testsuite/gna: add a test for Wuseless warning. For #1832Tristan Gingold2021-08-292-0/+26
* vhdl-canon: detect PSL assertion that cannot fail. For #1832Tristan Gingold2021-08-292-3/+17
* testsuite/synth: add a test for #1832Tristan Gingold2021-08-292-0/+29
* synth-vhdl_stmts: fix a crash on never triggered PSL assertion.Tristan Gingold2021-08-291-0/+6
* synth: improve result of is_positiveTristan Gingold2021-08-294-10/+15
* netlists-inference: improve location for dff.Tristan Gingold2021-08-291-1/+1
* synth: factorize code to create base instanceTristan Gingold2021-08-287-57/+104
* synthesis.adb: abstract instance_passesTristan Gingold2021-08-283-23/+34
* synth-environment: add subprograms for signals (preliminary work)Tristan Gingold2021-08-282-5/+110
* synth-memtype: export conversion functionsTristan Gingold2021-08-282-7/+9
* synth: add build2_concat2 and use it for vhdl concat.Tristan Gingold2021-08-283-4/+18
* ghdlsynth: add debug option for elaborationTristan Gingold2021-08-282-1/+8
* synth-vhdl_decls.adb: add commentsTristan Gingold2021-08-281-0/+4
* vhdl: handle foreign units in libraries and configurationTristan Gingold2021-08-283-24/+45
* errorout: do not display empty linesTristan Gingold2021-08-283-1/+14
* netlists-disp_verilog: handle initial value for idff and isignalTristan Gingold2021-08-281-8/+18
* pyGHDL.dom: improvements (#1848)Unai Martinez-Corral2021-08-275-19/+64
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| * Updated requirements to pyVHDLModel v0.12.0.Patrick Lehmann2021-08-271-2/+2
| * Handle sensitivity lists.Patrick Lehmann2021-08-271-4/+3
| * Added concurrent (PSL) assertion.Patrick Lehmann2021-08-263-5/+35
| * Translate sequential procedure calls.Patrick Lehmann2021-08-263-7/+8
| * Implemented handling off null statements.Patrick Lehmann2021-08-264-6/+21
* | testsuite/synth: add a test for #1850Tristan Gingold2021-08-273-0/+82
* | vhdl-parse: support for-generate in vunits. Fix #1850Tristan Gingold2021-08-271-2/+10
* | testsuite/synth: Add a test for ghdl/ghdl-yosys-plugin#154Tristan Gingold2021-08-272-0/+58
* | synth: do not remove signals with a keep attribute.Tristan Gingold2021-08-272-1/+31
* | std_names: add name keep.Tristan Gingold2021-08-273-183/+186
* | netlists-disp_verilog: fix handling of unconnected portTristan Gingold2021-08-261-3/+1
* | ghdlsynth.adb: fix a typoTristan Gingold2021-08-261-1/+1
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* testsuite/gna: add a test for #1832Tristan Gingold2021-08-262-0/+132
* PSL: handle inf in star repeat sequence. Fix #1832Tristan Gingold2021-08-269-11/+44
* testsuite/gna: add a reproducer for #1834Tristan Gingold2021-08-263-0/+59
* vhdl-evaluation: check integer evaluations fit in base type. Fix #1834Tristan Gingold2021-08-262-11/+37
* testsuite/synth: add a test for #1838Tristan Gingold2021-08-252-0/+48
* synth: reuse signal name while creating memories. Fix #1838Tristan Gingold2021-08-255-20/+34
* ortho/gcc: adjust and propagate to all gcc versions the change for #1845Tristan Gingold2021-08-256-1/+81
* testsuite/gna: add a testcase for #1844Tristan Gingold2021-08-252-0/+56
* vhdl-sem_types.adb: refine conditions for resolution functions.Tristan Gingold2021-08-251-3/+7
* ghdldrv: handle auxbase option in ortho/gcc. Fix #1845Tristan Gingold2021-08-242-10/+16
* testsuite/gna: add a test for #1814Tristan Gingold2021-08-243-0/+72
* testsuite/gna: add a test for #1837Tristan Gingold2021-08-242-0/+19
* vhdl-parse.adb: improve error recovery. For #1837Tristan Gingold2021-08-241-0/+2
* vhdl: remove iir_kind_anonymous_signal_declaration (now unused)Tristan Gingold2021-08-2423-643/+377
* vhdl-sem_specs: avoid ownership issue on default map aspect.Tristan Gingold2021-08-241-1/+4
* Changed Debian 'Buster' to 'Bullseye'Patrick Lehmann2021-08-233-3/+3
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| * Debian Bullseye was releasedumarcor2021-08-233-3/+3
* | Set black formatting to 120 chars per line.Patrick Lehmann2021-08-2333-757/+234
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| * pyGHDL/lsp: styleumarcor2021-08-231-6/+3
| * black: rerun, to pick pyproject settingsumarcor2021-08-2332-754/+232
| * add pyproject.tomlumarcor2021-08-231-0/+2
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