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| author | Patrick Lehmann <Patrick.Lehmann@plc2.de> | 2021-08-24 07:32:32 +0200 |
|---|---|---|
| committer | Patrick Lehmann <Patrick.Lehmann@plc2.de> | 2021-08-26 21:08:12 +0200 |
| commit | a6d0550e54a6243f4cc716ce98f348458c865fe8 (patch) | |
| tree | 190d33f6a602e5a99eb4f37931038ee696e15026 | |
| parent | 98b54bc3d1b54bfc5c03e74d049fb59db47df8db (diff) | |
| download | ghdl-a6d0550e54a6243f4cc716ce98f348458c865fe8.tar.gz ghdl-a6d0550e54a6243f4cc716ce98f348458c865fe8.tar.bz2 ghdl-a6d0550e54a6243f4cc716ce98f348458c865fe8.zip | |
Implemented handling off null statements.
| -rw-r--r-- | pyGHDL/dom/Sequential.py | 12 | ||||
| -rw-r--r-- | pyGHDL/dom/_Translate.py | 6 | ||||
| -rw-r--r-- | pyGHDL/dom/requirements.txt | 4 | ||||
| -rw-r--r-- | testsuite/pyunit/Current.vhdl | 5 |
4 files changed, 21 insertions, 6 deletions
diff --git a/pyGHDL/dom/Sequential.py b/pyGHDL/dom/Sequential.py index 9e1af5b32..70a16e4cd 100644 --- a/pyGHDL/dom/Sequential.py +++ b/pyGHDL/dom/Sequential.py @@ -54,6 +54,7 @@ from pyVHDLModel.SyntaxModel import ( SequentialProcedureCall as VHDLModel_SequentialProcedureCall, SequentialAssertStatement as VHDLModel_SequentialAssertStatement, SequentialReportStatement as VHDLModel_SequentialReportStatement, + NullStatement as VHDLModel_NullStatement, WaitStatement as VHDLModel_WaitStatement, Name, SequentialStatement, @@ -482,6 +483,17 @@ class SequentialReportStatement(VHDLModel_SequentialReportStatement, DOMMixin): @export +class NullStatement(VHDLModel_NullStatement, DOMMixin): + def __init__( + self, + waitNode: Iir, + label: str = None, + ): + super().__init__(label) + DOMMixin.__init__(self, waitNode) + + +@export class WaitStatement(VHDLModel_WaitStatement, DOMMixin): def __init__( self, diff --git a/pyGHDL/dom/_Translate.py b/pyGHDL/dom/_Translate.py index 723b13f69..5322760ab 100644 --- a/pyGHDL/dom/_Translate.py +++ b/pyGHDL/dom/_Translate.py @@ -41,7 +41,7 @@ from pyGHDL.dom.Sequential import ( SequentialReportStatement, SequentialAssertStatement, WaitStatement, - SequentialSimpleSignalAssignment, + SequentialSimpleSignalAssignment, NullStatement, ) from pyVHDLModel.SyntaxModel import ( ConstraintUnion, @@ -975,9 +975,7 @@ def GetSequentialStatementsFromChainedNodes( elif kind == nodes.Iir_Kind.Assertion_Statement: yield SequentialAssertStatement.parse(statement, label) elif kind == nodes.Iir_Kind.Null_Statement: - print( - "[NOT IMPLEMENTED] null statement (label: '{label}') at line {line}".format(label=label, line=pos.Line) - ) + yield NullStatement(statement, label) else: raise DOMException( "Unknown statement of kind '{kind}' in {entity} '{name}' at {file}:{line}:{column}.".format( diff --git a/pyGHDL/dom/requirements.txt b/pyGHDL/dom/requirements.txt index d296f0e96..fbc6a6f6e 100644 --- a/pyGHDL/dom/requirements.txt +++ b/pyGHDL/dom/requirements.txt @@ -1,4 +1,4 @@ -r ../libghdl/requirements.txt -pyVHDLModel==0.11.5 -#https://github.com/VHDL/pyVHDLModel/archive/dev.zip#pyVHDLModel +#pyVHDLModel==0.12.0 +https://github.com/VHDL/pyVHDLModel/archive/dev.zip#pyVHDLModel diff --git a/testsuite/pyunit/Current.vhdl b/testsuite/pyunit/Current.vhdl index b4906e211..c02493c21 100644 --- a/testsuite/pyunit/Current.vhdl +++ b/testsuite/pyunit/Current.vhdl @@ -210,6 +210,11 @@ begin constant G7 : boolean := False; begin inst: component Case5689Dummy; + process + begin + null; + wait; + end process; when others => constant G8 : boolean := False; |