iCE40/ghdl - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
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\| *	Updated setup.py to use pyTooling.Packaging.	Patrick Lehmann	2021-12-12	6	-109/+28
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\| *	Changed export decorator from pydecor to pyTooling.Decorators	Patrick Lehmann	2021-12-12	52	-62/+61
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*	Fix opening files relative to the current vhdl	Matt Johnston	2021-12-07	1	-0/+2
\| \| \| \| \| \| \|	This regressed in 86fd1ab3 ("synth: do full elaboration before synthesis") 1 Nov 2021
*	testsuite/synth: add a test for #938	Tristan Gingold	2021-12-06	4	-0/+109
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*	synth: add --latches option to enable latches. Fix #938	Tristan Gingold	2021-12-06	3	-1/+11
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*	Update .editorconfig with settings for Ada files	std-max	2021-12-06	1	-0/+4
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*	testsuite/gna: add a test for conformance rules	Tristan Gingold	2021-12-03	2	-0/+24
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*	vhdl-sem.adb: fix incorrect check for conformance rules	Tristan Gingold	2021-12-03	1	-1/+3
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*	testsuite/synth: add a test for #1926	Tristan Gingold	2021-11-29	3	-0/+485
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*	synth/elab-vhdl_expr: handle slices and indexed names. Fix #1926	Tristan Gingold	2021-11-29	1	-19/+11
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*	testsuite/synth: avoid use of verilog identifiers	Tristan Gingold	2021-11-28	6	-20/+20
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*	synth memories: also accept constant signal as memory initial value	Tristan Gingold	2021-11-28	2	-4/+9
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*	elab-vhdl_objtypes.adb: add an assertion	Tristan Gingold	2021-11-28	1	-0/+2
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*	elab-vhdl_insts.adb: do not try to elaborate foreign instances twice	Tristan Gingold	2021-11-28	1	-1/+6
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*	synth: adjustments for foreign_module	Tristan Gingold	2021-11-28	2	-3/+12
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*	synth: add a hook to resolve foreign instantiation names	Tristan Gingold	2021-11-28	2	-0/+8
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*	synth-vhdl_insts.adb: split synth_Instantiate_Module	Tristan Gingold	2021-11-28	1	-14/+26
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*	synth: add hooks to support elaboration of foreign instances	Tristan Gingold	2021-11-28	10	-32/+108
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*	vhdl-parse: improve error message for empty records	Tristan Gingold	2021-11-28	1	-29/+33
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*	testsuite/gna: add test from #1924	Tristan Gingold	2021-11-27	4	-0/+100
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*	testsuite/gna: add a test for #1914	Tristan Gingold	2021-11-24	6	-0/+204
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*	vhdl/translate: handle target aggregate with unbounded names. Fix #1914	Tristan Gingold	2021-11-24	4	-22/+75
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*	testsuite/gna: add a test for #1919	Tristan Gingold	2021-11-21	3	-0/+22
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*	vhdl-sem_decls: avoid a crash on invalid alias name. Fix #1919	Tristan Gingold	2021-11-21	1	-0/+10
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*	testsuite/synth: add a test for #1920	Tristan Gingold	2021-11-21	3	-0/+68
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*	synth-vhdl_expr: emit an error if use of a signal during elaboration. Fix #1920	Tristan Gingold	2021-11-21	1	-0/+7
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*	synth: put direction into port desc	Tristan Gingold	2021-11-17	8	-31/+30
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*	synth: use a global table for instances attributes	Tristan Gingold	2021-11-17	6	-168/+117
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*	synth: renaming to instance_attributes.	Tristan Gingold	2021-11-17	11	-66/+72
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*	synth/netlists-disp_verilog: display port attributes	Tristan Gingold	2021-11-17	1	-18/+42
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*	synth: add ports attributes	Tristan Gingold	2021-11-17	3	-0/+120
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*	vhdl-utils.adb: minor refactoring	Tristan Gingold	2021-11-17	1	-7/+3
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*	grt: refactoring to fix build failure. For #1913	Tristan Gingold	2021-11-17	5	-394/+443
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*	Add comments	Tristan Gingold	2021-11-17	2	-0/+4
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*	vhdl-evaluation: use grt to compute value attribute for integers.	Tristan Gingold	2021-11-17	3	-33/+97
\| \| \| \|	For #1913
*	grt/Makefile.inc: add a dependency for grt-cgnatrts.	Tristan Gingold	2021-11-16	1	-2/+3
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*	testsuite/synth: add a test for #1912	Tristan Gingold	2021-11-16	2	-0/+82
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*	synth: defer instantations elaboration to handle recursion. Fix #1912	Tristan Gingold	2021-11-16	2	-15/+110
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*	testsuite/gna: add scripts to generate 1d/2d aggregates	Tristan Gingold	2021-11-16	2	-0/+30
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*	testsuite/gna: add a test for #1913	Tristan Gingold	2021-11-15	2	-0/+123
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*	vhdl-evaluation: catch bad parameter for value attribute. Fix #1913	Tristan Gingold	2021-11-15	1	-1/+7
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*	testsuite/gna: add a test for previous commit	Tristan Gingold	2021-11-15	4	-0/+83
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*	vhdl-sem_expr: improve code generation for multi-dim aggregates	Tristan Gingold	2021-11-15	1	-3/+3
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*	testsuite/synth: add a test for syn_black_box	Tristan Gingold	2021-11-13	2	-0/+23
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*	synth: handle syn_black_box attribute in vhdl architectures	Tristan Gingold	2021-11-13	1	-10/+75
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*	testsuite/synth: add a test for #1911	Tristan Gingold	2021-11-13	3	-0/+315
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*	synth: add exec_name_subtype. Fix #1911	Tristan Gingold	2021-11-13	3	-4/+52
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*	testsuite/synth: add a test for black boxes	Tristan Gingold	2021-11-12	4	-0/+80
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*	testsuite/synth: adjust test after previous commit	Tristan Gingold	2021-11-12	4	-2/+20
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*	synth: do not display black boxes	Tristan Gingold	2021-11-12	1	-1/+6
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