index
:
iCE40/ghdl
master
[no description]
about
summary
refs
log
tree
commit
diff
stats
log msg
author
committer
range
Commit message (
Collapse
)
Author
Age
Files
Lines
*
synth: rename vhdl.annotations to elab.vhdl_annotations
Tristan Gingold
2022-09-19
8
-18
/
+20
|
*
synth: rework subprogram associations (WIP)
Tristan Gingold
2022-09-19
3
-42
/
+87
|
*
synth-vhdl_stmts: minor renaming
Tristan Gingold
2022-09-18
4
-12
/
+12
|
*
synth: fix assert failure on attribute specification
Tristan Gingold
2022-09-18
1
-1
/
+5
|
*
simul: handle individual port associations with expressions
Tristan Gingold
2022-09-18
1
-1
/
+5
|
*
simul: handle type conversions in port associations
Tristan Gingold
2022-09-18
3
-49
/
+57
|
*
synth: handle open variable association
Tristan Gingold
2022-09-17
1
-22
/
+31
|
*
simul: fix resolved association
Tristan Gingold
2022-09-17
2
-2
/
+3
|
*
simul: use synth_declarations for processes and procedures
Tristan Gingold
2022-09-17
4
-18
/
+15
|
*
synth: factorize code (reuse synth_constant_declaration)
Tristan Gingold
2022-09-17
8
-71
/
+22
|
*
synth: handle protected types in subprograms
Tristan Gingold
2022-09-17
3
-38
/
+53
|
*
synth: improve file handling (skip extra data, errors)
Tristan Gingold
2022-09-17
3
-3
/
+53
|
*
synth: finalize files
Tristan Gingold
2022-09-17
3
-4
/
+30
|
*
synth: handle read length on text files
Tristan Gingold
2022-09-17
1
-16
/
+40
|
*
synth: handle incomplete types
Tristan Gingold
2022-09-17
6
-24
/
+87
|
*
synth: handle individual generic associations
Tristan Gingold
2022-09-17
1
-5
/
+35
|
*
synth: factorize code with synth_assignment_prefix
Tristan Gingold
2022-09-16
1
-75
/
+15
|
*
synth: preliminary work to factorize code
Tristan Gingold
2022-09-16
6
-52
/
+69
|
*
simul: handle active attribute
Tristan Gingold
2022-09-16
4
-11
/
+58
|
*
synth: handle val attribute for static bit/logic values
Tristan Gingold
2022-09-16
1
-0
/
+3
|
*
simul: improve support of concurrent procedure call
Tristan Gingold
2022-09-16
1
-1
/
+20
|
*
simul: improve error handling during elaboration
Tristan Gingold
2022-09-16
2
-5
/
+6
|
*
synth: improve handling of complex types
Tristan Gingold
2022-09-15
4
-8
/
+30
|
*
synth: handle vhdl-87 files
Tristan Gingold
2022-09-15
2
-2
/
+14
|
*
synth: handle access subtypes
Tristan Gingold
2022-09-15
2
-1
/
+9
|
*
synth: handle read for files of unconstrained arrays
Tristan Gingold
2022-09-15
3
-1
/
+54
|
*
simul: handle more signals types
Tristan Gingold
2022-09-15
2
-23
/
+128
|
*
testsuite/gna: add a test for #2189
Tristan Gingold
2022-09-15
4
-0
/
+69
|
*
trans-chap7: fix choice of exp. Fix #2189
Tristan Gingold
2022-09-15
1
-3
/
+3
|
*
ortho/mcode: add reg move for ret. Fix #2189
Tristan Gingold
2022-09-15
2
-7
/
+17
|
*
synth-vhdl_stmts: handle attribute names in expressions
Tristan Gingold
2022-09-14
1
-1
/
+3
|
*
simul: handle --expect-failure for elaboration
Tristan Gingold
2022-09-14
3
-11
/
+15
|
*
synth: detect overflow in static exponentiation
Tristan Gingold
2022-09-14
6
-76
/
+266
|
|
|
|
src/grt: extract grt.arith from grt.lib
*
synth: add bounds check for float-integer type conversion
Tristan Gingold
2022-09-12
1
-2
/
+21
|
*
simul: factorize code for conversion functions
Tristan Gingold
2022-09-12
1
-19
/
+6
|
*
simul: do not consider signal parameters as dynamic values
Tristan Gingold
2022-09-12
3
-1
/
+9
|
*
testsuite/synth: add tests for succ/pred/leftof/rightof attributes
Tristan Gingold
2022-09-12
9
-0
/
+113
|
*
synth: handle succ,pred,leftof,rightof attributes
Tristan Gingold
2022-09-12
1
-0
/
+95
|
*
synth: improve handling of top-level interfaces subtype
Tristan Gingold
2022-09-11
7
-20
/
+58
|
*
synth: initialize out parameters of procedures
Tristan Gingold
2022-09-11
1
-2
/
+9
|
*
simul: move assertions (not to trigger in case of errors)
Tristan Gingold
2022-09-11
1
-3
/
+3
|
*
simul: optimize resolution call only for std_logic
Tristan Gingold
2022-09-11
1
-5
/
+11
|
*
synth: fix and add checks for memory management.
Tristan Gingold
2022-09-10
16
-116
/
+362
|
*
testsuite/synth: add a test with uninitialized shared variable
Tristan Gingold
2022-09-08
3
-1
/
+101
|
*
simul: add support for protected objects
Tristan Gingold
2022-09-08
12
-23
/
+267
|
*
testsuite/synth: add a test for #2187
Tristan Gingold
2022-09-08
5
-0
/
+410
|
*
elab-vhdl_objtypes: handle bounded array base type. Fix #2187
Tristan Gingold
2022-09-08
1
-1
/
+2
|
*
elab-vhdl_values: factorize code
Tristan Gingold
2022-09-07
6
-29
/
+16
|
*
simul: do not propagate errors from resolution function
Tristan Gingold
2022-09-07
1
-0
/
+3
|
*
synth-vhdl_stmts: fix handling of copyback parameters
Tristan Gingold
2022-09-07
3
-26
/
+38
|
[next]