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* doc: space cleanupumarcor2021-12-151-1/+1
* configure: update version check regexpumarcor2021-12-151-6/+6
* pyproject: add section 'build-system', include pyTooling.Packagingumarcor2021-12-151-0/+8
* Merge branch 'ghdl:master' into paebbels/pyGHDL-updatesPatrick Lehmann2021-12-1531-90/+648
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| * testsuite/synth: provide a testcase for #412Tristan Gingold2021-12-156-0/+328
| * synth: handle interface type in generics. For #412Tristan Gingold2021-12-154-28/+49
| * mcode: generate and register .eh_frame on linux x86/64Tristan Gingold2021-12-1414-11/+179
| * ghdldrv: handle generic overrides on foreign unitsTristan Gingold2021-12-134-50/+75
| * testsuite/gna: add a test for previous commitTristan Gingold2021-12-132-0/+15
| * vhdl-sem_expr.adb: avoid a crash after forced analysisTristan Gingold2021-12-131-1/+2
* | One more dependency.Patrick Lehmann2021-12-141-1/+1
* | Added entry points.Patrick Lehmann2021-12-142-2/+6
* | Install pyTooling.Packaging together with pyGHDLPatrick Lehmann2021-12-141-1/+3
* | Fixed license in `setup.py`.Patrick Lehmann2021-12-132-2/+3
* | Bumped dependencies.Patrick Lehmann2021-12-133-3/+3
* | Bumped version of pyTooling.Packaging to v0.3.2.Patrick Lehmann2021-12-122-2/+2
* | Adjusted configure script.Patrick Lehmann2021-12-125-17/+18
* | Using pyTooling.Packaging in conf.py.Patrick Lehmann2021-12-121-22/+14
* | Updated setup.py to use pyTooling.Packaging.Patrick Lehmann2021-12-126-109/+28
* | Changed export decorator from pydecor to pyTooling.DecoratorsPatrick Lehmann2021-12-1252-62/+61
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* Fix opening files relative to the current vhdlMatt Johnston2021-12-071-0/+2
* testsuite/synth: add a test for #938Tristan Gingold2021-12-064-0/+109
* synth: add --latches option to enable latches. Fix #938Tristan Gingold2021-12-063-1/+11
* Update .editorconfig with settings for Ada filesstd-max2021-12-061-0/+4
* testsuite/gna: add a test for conformance rulesTristan Gingold2021-12-032-0/+24
* vhdl-sem.adb: fix incorrect check for conformance rulesTristan Gingold2021-12-031-1/+3
* testsuite/synth: add a test for #1926Tristan Gingold2021-11-293-0/+485
* synth/elab-vhdl_expr: handle slices and indexed names. Fix #1926Tristan Gingold2021-11-291-19/+11
* testsuite/synth: avoid use of verilog identifiersTristan Gingold2021-11-286-20/+20
* synth memories: also accept constant signal as memory initial valueTristan Gingold2021-11-282-4/+9
* elab-vhdl_objtypes.adb: add an assertionTristan Gingold2021-11-281-0/+2
* elab-vhdl_insts.adb: do not try to elaborate foreign instances twiceTristan Gingold2021-11-281-1/+6
* synth: adjustments for foreign_moduleTristan Gingold2021-11-282-3/+12
* synth: add a hook to resolve foreign instantiation namesTristan Gingold2021-11-282-0/+8
* synth-vhdl_insts.adb: split synth_Instantiate_ModuleTristan Gingold2021-11-281-14/+26
* synth: add hooks to support elaboration of foreign instancesTristan Gingold2021-11-2810-32/+108
* vhdl-parse: improve error message for empty recordsTristan Gingold2021-11-281-29/+33
* testsuite/gna: add test from #1924Tristan Gingold2021-11-274-0/+100
* testsuite/gna: add a test for #1914Tristan Gingold2021-11-246-0/+204
* vhdl/translate: handle target aggregate with unbounded names. Fix #1914Tristan Gingold2021-11-244-22/+75
* testsuite/gna: add a test for #1919Tristan Gingold2021-11-213-0/+22
* vhdl-sem_decls: avoid a crash on invalid alias name. Fix #1919Tristan Gingold2021-11-211-0/+10
* testsuite/synth: add a test for #1920Tristan Gingold2021-11-213-0/+68
* synth-vhdl_expr: emit an error if use of a signal during elaboration. Fix #1920Tristan Gingold2021-11-211-0/+7
* synth: put direction into port descTristan Gingold2021-11-178-31/+30
* synth: use a global table for instances attributesTristan Gingold2021-11-176-168/+117
* synth: renaming to instance_attributes.Tristan Gingold2021-11-1711-66/+72
* synth/netlists-disp_verilog: display port attributesTristan Gingold2021-11-171-18/+42
* synth: add ports attributesTristan Gingold2021-11-173-0/+120
* vhdl-utils.adb: minor refactoringTristan Gingold2021-11-171-7/+3
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