| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | synth: handle guard signal in expressions | Tristan Gingold | 2022-09-28 | 2 | -0/+2 |
| * | simul: fix handling of labels in next/exit statements | Tristan Gingold | 2022-09-28 | 1 | -4/+13 |
| * | synth: handle null-range loops | Tristan Gingold | 2022-09-28 | 5 | -21/+40 |
| * | testsuite/gna: add a test for #2201 | Tristan Gingold | 2022-09-28 | 2 | -0/+39 |
| * | vhdl-sem: avoid a crash after error. Fix #2201 | Tristan Gingold | 2022-09-28 | 1 | -0/+1 |
| * | synth: handle names in record aggregate targets | Tristan Gingold | 2022-09-28 | 1 | -0/+12 |
| * | synth: handle array target aggregate | Tristan Gingold | 2022-09-27 | 1 | -2/+6 |
| * | synth: handle error on variable default value | Tristan Gingold | 2022-09-27 | 1 | -0/+5 |
| * | simul: handle null signal assignments | Tristan Gingold | 2022-09-27 | 1 | -12/+36 |
| * | synth-vhdl_eval: handle nor, nand | Tristan Gingold | 2022-09-26 | 1 | -0/+21 |
| * | simul-vhdl_elab: avoid a crash for null-range signals | Tristan Gingold | 2022-09-26 | 1 | -10/+14 |
| * | synth: handle attributes in configurations | Tristan Gingold | 2022-09-26 | 4 | -3/+16 |
| * | synth: improve error checks (type conversion, string literals) | Tristan Gingold | 2022-09-25 | 3 | -33/+37 |
| * | synth: rework error procedure, always pass the instance | Tristan Gingold | 2022-09-25 | 17 | -254/+406 |
| * | synth-vhdl_eval: handle vhdl-87 array array concatenation | Tristan Gingold | 2022-09-25 | 1 | -2/+31 |
| * | testsuite/gna: add a test for #2196 | Tristan Gingold | 2022-09-25 | 2 | -0/+55 |
| * | vhdl-sem_decls: handle protected type subtypes | Tristan Gingold | 2022-09-25 | 1 | -1/+4 |
| * | testsuite/gna: add a test for #2198 | Tristan Gingold | 2022-09-25 | 2 | -0/+60 |
| * | vhdl-sem_names: handle architecture bodies in sem_denoting_name | Tristan Gingold | 2022-09-25 | 1 | -1/+2 |
| * | synth-vhdl_stmts: fix missing newline in default assertion messages | Tristan Gingold | 2022-09-25 | 1 | -3/+3 |
| * | synth: handle default expression for IN variables in assocs | Tristan Gingold | 2022-09-25 | 1 | -4/+10 |
| * | synth: handle selected names in targets | Tristan Gingold | 2022-09-25 | 1 | -1/+2 |
| * | synth-vhdl_eval: handle null-null in array concatenations | Tristan Gingold | 2022-09-25 | 1 | -0/+6 |
| * | simul: gather disconnection specifications, create guard signal | Tristan Gingold | 2022-09-25 | 4 | -36/+194 |
| * | synth: ignore groups and group templates | Tristan Gingold | 2022-09-25 | 3 | -1/+15 |
| * | grt: do not initialial GUARD signals on creation. | Tristan Gingold | 2022-09-25 | 1 | -1/+4 |
| * | synth: handle attribute names | Tristan Gingold | 2022-09-25 | 1 | -13/+16 |
| * | synth: handle individual subprogram associations for expressions | Tristan Gingold | 2022-09-25 | 1 | -55/+61 |
| * | simul: handle empty procedures | Tristan Gingold | 2022-09-25 | 1 | -1/+9 |
| * | synth: rework association conversions | Tristan Gingold | 2022-09-25 | 3 | -62/+75 |
| * | synth-vhdl_stmts: rework for subprogram associations (WIP) | Tristan Gingold | 2022-09-25 | 1 | -57/+36 |
| * | synth-vhdl_stmts: support of individual paramater associations (WIP) | Tristan Gingold | 2022-09-25 | 2 | -106/+238 |
| * | simul: reuse drivers extraction from elaboration | Tristan Gingold | 2022-09-25 | 2 | -74/+26 |
| * | synth-vhdl_stmts: refactore synth_subprogram_associations | Tristan Gingold | 2022-09-25 | 1 | -49/+52 |
| * | suite_driver.sh: print a message in case of failure | Tristan Gingold | 2022-09-25 | 1 | -0/+1 |
| * | synth-vhdl_stmts: refactore | Tristan Gingold | 2022-09-25 | 1 | -23/+32 |
| * | synth-vhdl_stmts: refactoring | Tristan Gingold | 2022-09-25 | 1 | -189/+208 |
| * | synth-vhdl_stmts: rework in progress of subprogram associations | Tristan Gingold | 2022-09-25 | 1 | -108/+115 |
| * | pyGHDL: added missing type annotations. Fix #2192 (#2195) | fhuemer | 2022-09-23 | 1 | -2/+2 |
| * | synth-vhdl_insts: move pragma unreferenced | Tristan Gingold | 2022-09-21 | 1 | -1/+2 |
| * | configure: tentatively enable llvm 15 | Tristan Gingold | 2022-09-21 | 1 | -0/+1 |
| * | synth: simplify elab-vhdl_annotations | Tristan Gingold | 2022-09-19 | 2 | -51/+3 |
| * | synth: simplify elab-vhdl_annotations | Tristan Gingold | 2022-09-19 | 5 | -197/+31 |
| * | synth: rename vhdl.annotations to elab.vhdl_annotations | Tristan Gingold | 2022-09-19 | 8 | -18/+20 |
| * | synth: rework subprogram associations (WIP) | Tristan Gingold | 2022-09-19 | 3 | -42/+87 |
| * | synth-vhdl_stmts: minor renaming | Tristan Gingold | 2022-09-18 | 4 | -12/+12 |
| * | synth: fix assert failure on attribute specification | Tristan Gingold | 2022-09-18 | 1 | -1/+5 |
| * | simul: handle individual port associations with expressions | Tristan Gingold | 2022-09-18 | 1 | -1/+5 |
| * | simul: handle type conversions in port associations | Tristan Gingold | 2022-09-18 | 3 | -49/+57 |
| * | synth: handle open variable association | Tristan Gingold | 2022-09-17 | 1 | -22/+31 |
