index
:
iCE40/ghdl
master
[no description]
about
summary
refs
log
tree
commit
diff
stats
log msg
author
committer
range
Commit message (
Expand
)
Author
Age
Files
Lines
...
*
grt: add modules in ghdl_main instead of grt-main
Tristan Gingold
2023-01-05
4
-7
/
+9
*
synth-vhdl_decls: manually elaborate protected type body
Tristan Gingold
2023-01-04
2
-6
/
+27
*
vhdl-sem_expr: extract is_expression
Tristan Gingold
2023-01-04
2
-18
/
+30
*
vhdl-errors(disp_node): fix a crash on protected type body
Tristan Gingold
2023-01-04
1
-1
/
+2
*
synth: detect null access dereference, fix offset.
Tristan Gingold
2023-01-04
2
-4
/
+19
*
elab-vhdl_debug: avoid a crash on error in print
Tristan Gingold
2023-01-04
1
-5
/
+9
*
elab-vhdl_debug: handle protected type body, nested packages
Tristan Gingold
2023-01-04
1
-5
/
+11
*
elab-vhdl_debug: add pheap command, improve access display
Tristan Gingold
2023-01-04
1
-1
/
+32
*
elab-debugger: improve backtrace, source display
Tristan Gingold
2023-01-04
1
-6
/
+19
*
synth-ieee-numeric_std: avoid a crash on mul with meta-values
Tristan Gingold
2023-01-04
1
-19
/
+29
*
vhdl-sem_inst: handle suspend_state
Tristan Gingold
2023-01-04
8
-186
/
+333
*
ghdlsimul: do late semantic checks
Tristan Gingold
2023-01-04
1
-1
/
+19
*
synth: check length of selector in case statement
Tristan Gingold
2023-01-04
1
-0
/
+4
*
synth: fix handling of target aggregate in conditional variable assignment
Tristan Gingold
2023-01-04
1
-3
/
+4
*
simul: handle force/release signal assignments
Tristan Gingold
2023-01-03
6
-18
/
+221
*
synth: handle more 2008 aggregates
Tristan Gingold
2023-01-03
3
-11
/
+43
*
synth-vhdl_aggr: minor renaming
Tristan Gingold
2023-01-03
1
-8
/
+9
*
synth: introduce type_array_unbounded
Tristan Gingold
2023-01-03
13
-48
/
+143
*
synth: fix handling of record subtypes for objects
Tristan Gingold
2023-01-03
1
-0
/
+1
*
synth: adjust exec_name_subtype for function calls
Tristan Gingold
2023-01-03
1
-0
/
+7
*
simul: skip psl default clock in declarations
Tristan Gingold
2023-01-03
1
-0
/
+1
*
synth: add support of interface subprogram
Tristan Gingold
2023-01-03
3
-31
/
+33
*
synth: improve support of vhdl-08 arrays
Tristan Gingold
2023-01-02
3
-13
/
+40
*
synth: fix to_string for character
Tristan Gingold
2023-01-02
2
-1
/
+12
*
synth: add support for nested packages
Tristan Gingold
2023-01-02
3
-19
/
+87
*
synth: elaborate case generate statements
Tristan Gingold
2023-01-01
6
-18
/
+74
*
simul: handle nested packages
Tristan Gingold
2023-01-01
3
-1
/
+19
*
testsuite/gna: add a test for #2288
Tristan Gingold
2022-12-31
2
-0
/
+45
*
trans-chap7: handle unbounded expressions in aggregates.
Tristan Gingold
2022-12-31
1
-24
/
+39
*
elab-vhdl_expr: fix a crash on simple aggregate
Tristan Gingold
2022-12-31
1
-8
/
+2
*
synth: handle string literals in debug
Tristan Gingold
2022-12-31
1
-1
/
+2
*
synth: add statement in context, adjust path/instance name attributes
Tristan Gingold
2022-12-31
10
-43
/
+92
*
grt-files_operations: allow last line without EOL
Tristan Gingold
2022-12-31
1
-1
/
+4
*
Merge pull request #2289 from Paebbels/paebbels/pyVHDLModel-updates
tgingold
2022-12-31
35
-224
/
+507
|
\
|
*
Formatting by black.
Patrick Lehmann
2022-12-30
4
-6
/
+24
|
*
Bumped dependency to pyVHDLModel to v0.20.2
Patrick Lehmann
2022-12-30
2
-3
/
+3
|
*
Fixed handling of Use clauses in packages.
Patrick Lehmann
2022-12-30
1
-2
/
+5
|
*
Bumped dependency to pyVHDLModel to v0.20.0
Patrick Lehmann
2022-12-30
1
-1
/
+1
|
*
Improved VHDL example project.
Patrick Lehmann
2022-12-29
8
-62
/
+77
|
*
Added Get***Symbol functions. Improved Symbol handling.
Patrick Lehmann
2022-12-29
7
-89
/
+192
|
*
Fixed duplicate testcase name (Vital).
Patrick Lehmann
2022-12-27
1
-1
/
+1
|
*
Fixed context and package names and their references in VHDL example code.
Patrick Lehmann
2022-12-27
9
-11
/
+20
|
*
Fixed glob pattern in DOM CLI test program.
Patrick Lehmann
2022-12-27
1
-2
/
+2
|
*
Improved prettyprint.
Patrick Lehmann
2022-12-27
1
-12
/
+12
|
*
Implemented GetContextSymbol and fixed how ContextReferenceSymbols are created.
Patrick Lehmann
2022-12-27
2
-5
/
+14
|
*
Formatting by black.
Patrick Lehmann
2022-12-26
4
-8
/
+13
|
*
Improved StopWatch testcase.
Patrick Lehmann
2022-12-26
6
-52
/
+51
|
*
Replaced specific code with routines from pyVHDLModel.
Patrick Lehmann
2022-12-26
2
-11
/
+21
|
*
Bumped dependecy to pyVHDLModel and added analysis time measurements.
Patrick Lehmann
2022-12-26
2
-1
/
+16
|
*
More adjustments to new symbols.
Patrick Lehmann
2022-12-26
3
-16
/
+21
[prev]
[next]