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| author | Tristan Gingold <tgingold@free.fr> | 2023-01-04 08:01:59 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2023-01-04 08:01:59 +0100 |
| commit | a4d2654ea1136b3861960d6b5f82cdc3b36efab2 (patch) | |
| tree | d626ea7dd2d7611e2a4a093a1eea772a9f24751d | |
| parent | 2f48848575261265b1c37efe10ded83ccff11aa2 (diff) | |
| download | ghdl-a4d2654ea1136b3861960d6b5f82cdc3b36efab2.tar.gz ghdl-a4d2654ea1136b3861960d6b5f82cdc3b36efab2.tar.bz2 ghdl-a4d2654ea1136b3861960d6b5f82cdc3b36efab2.zip | |
synth: fix handling of target aggregate in conditional variable assignment
| -rw-r--r-- | src/synth/synth-vhdl_stmts.adb | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/src/synth/synth-vhdl_stmts.adb b/src/synth/synth-vhdl_stmts.adb index 116dafd03..794f4ca97 100644 --- a/src/synth/synth-vhdl_stmts.adb +++ b/src/synth/synth-vhdl_stmts.adb @@ -884,8 +884,8 @@ package body Synth.Vhdl_Stmts is (Inst : Synth_Instance_Acc; Stmt : Node) is Ctxt : constant Context_Acc := Get_Build (Inst); - Target : constant Node := Get_Target (Stmt); Marker : Mark_Type; + Targ : Target_Info; Targ_Type : Type_Acc; Cond : Node; Ce : Node; @@ -895,7 +895,8 @@ package body Synth.Vhdl_Stmts is Cond_Tri : Tri_State_Type; begin Mark_Expr_Pool (Marker); - Targ_Type := Get_Subtype_Object (Inst, Get_Type (Target)); + Targ := Synth_Target (Inst, Get_Target (Stmt)); + Targ_Type := Targ.Targ_Type; First := No_Valtyp; Last := No_Net; Ce := Get_Conditional_Expression_Chain (Stmt); @@ -957,7 +958,7 @@ package body Synth.Vhdl_Stmts is Ce := Get_Chain (Ce); end loop; - Synth_Assignment (Inst, Target, First, Stmt); + Synth_Assignment (Inst, Targ, First, Stmt); Release_Expr_Pool (Marker); end Synth_Conditional_Variable_Assignment; |