synth: handle more 2008 aggregates

3 files changed, 43 insertions, 11 deletions

diff --git a/src/synth/elab-vhdl_objtypes.adb b/src/synth/elab-vhdl_objtypes.adb
index b8c154ed2..c00f73478 100644
--- a/src/synth/elab-vhdl_objtypes.adb
+++ b/src/synth/elab-vhdl_objtypes.adb
@@ -526,8 +526,9 @@ package body Elab.Vhdl_Objtypes is
 
    function Get_Array_Bound (Typ : Type_Acc) return Bound_Type is
    begin
-      case Typ.Kind is
+      case Type_Vectors_Arrays (Typ.Kind) is
          when Type_Vector
+           | Type_Array_Unbounded
            | Type_Array =>
             return Typ.Abound;
          when others =>
@@ -723,10 +724,11 @@ package body Elab.Vhdl_Objtypes is
 
    function Get_Array_Flat_Length (Typ : Type_Acc) return Iir_Index32 is
    begin
-      case Typ.Kind is
+      case Type_Vectors_Arrays (Typ.Kind) is
          when Type_Vector =>
             return Iir_Index32 (Typ.Abound.Len);
-         when Type_Array =>
+         when Type_Array
+           | Type_Array_Unbounded =>
             declare
                Len : Uns32;
                T : Type_Acc;
diff --git a/src/synth/elab-vhdl_objtypes.ads b/src/synth/elab-vhdl_objtypes.ads
index f45f1051d..99f8434e7 100644
--- a/src/synth/elab-vhdl_objtypes.ads
+++ b/src/synth/elab-vhdl_objtypes.ads
@@ -72,13 +72,15 @@ package Elab.Vhdl_Objtypes is
       Type_Logic,
       Type_Discrete,
       Type_Float,
-      Type_Vector,
-      Type_Unbounded_Vector,
 
       --  A slice is for a slice of vector with dynamic bounds.  So the bounds
       --  of the result aren't known, but its width is.
       Type_Slice,
 
+      --  A vector is an array a net type.
+      Type_Vector,
+      Type_Unbounded_Vector,
+
       --  Fully bounded array.
       Type_Array,
 
@@ -104,6 +106,8 @@ package Elab.Vhdl_Objtypes is
    subtype Type_Scalars is Type_Kind range Type_Bit .. Type_Float;
    subtype Type_Records is Type_Kind range
      Type_Unbounded_Record .. Type_Record;
+   subtype Type_Vectors_Arrays is Type_Kind range
+     Type_Vector .. Type_Unbounded_Array;
    subtype Type_Arrays is Type_Kind range
      Type_Array .. Type_Unbounded_Array;
    subtype Type_Vectors is Type_Kind range
diff --git a/src/synth/synth-vhdl_aggr.adb b/src/synth/synth-vhdl_aggr.adb
index d0d277736..a0d9ed522 100644
--- a/src/synth/synth-vhdl_aggr.adb
+++ b/src/synth/synth-vhdl_aggr.adb
@@ -82,7 +82,8 @@ package body Synth.Vhdl_Aggr is
       case Typ.Kind is
          when Type_Vector =>
             return (1 => 1);
-         when Type_Array =>
+         when Type_Array
+           | Type_Array_Unbounded =>
             declare
                T : Type_Acc;
                Ndim : Dim_Type;
@@ -444,6 +445,7 @@ package body Synth.Vhdl_Aggr is
       Tab_Res : Valtyp_Array_Acc;
       Const_P : Boolean;
       Err_P : Boolean;
+      Res_Typ : Type_Acc;
       Res : Valtyp;
    begin
       Tab_Res := new Valtyp_Array'(1 .. Nat32 (Flen) => No_Valtyp);
@@ -454,13 +456,25 @@ package body Synth.Vhdl_Aggr is
          return No_Valtyp;
       end if;
 
-      --  TODO: check all element types have the same bounds ?
+
+      case Type_Vectors_Arrays (Aggr_Typ.Kind) is
+         when Type_Array
+           | Type_Vector =>
+            Res_Typ := Aggr_Typ;
+         when Type_Array_Unbounded =>
+            --  TODO: check all element types have the same bounds ?
+            Res_Typ := Create_Array_From_Array_Unbounded
+              (Aggr_Typ, Tab_Res (1).Typ);
+         when Type_Unbounded_Vector
+           | Type_Unbounded_Array =>
+            raise Internal_Error;
+      end case;
 
       if Const_P then
          declare
             Off : Size_Type;
          begin
-            Res := Create_Value_Memory (Aggr_Typ, Current_Pool);
+            Res := Create_Value_Memory (Res_Typ, Current_Pool);
             Off := 0;
             for I in Tab_Res'Range loop
                if Tab_Res (I).Val /= null then
@@ -469,11 +483,11 @@ package body Synth.Vhdl_Aggr is
                   Off := Off + Tab_Res (I).Typ.Sz;
                end if;
             end loop;
-            pragma Assert (Off = Aggr_Typ.Sz);
+            pragma Assert (Off = Res_Typ.Sz);
          end;
       else
          Res := Create_Value_Net
-           (Valtyp_Array_To_Net (Ctxt, Tab_Res.all), Aggr_Typ);
+           (Valtyp_Array_To_Net (Ctxt, Tab_Res.all), Res_Typ);
       end if;
 
       Free_Valtyp_Array (Tab_Res);
@@ -552,7 +566,19 @@ package body Synth.Vhdl_Aggr is
             begin
                Res_Type := Synth_Subtype_Indication
                  (Syn_Inst, Get_Type (Aggr));
-               return Synth_Aggregate_Array (Syn_Inst, Aggr, Res_Type);
+               case Res_Type.Kind is
+                  when Type_Array
+                    | Type_Array_Unbounded
+                    | Type_Vector =>
+                     return Synth_Aggregate_Array (Syn_Inst, Aggr, Res_Type);
+                  when Type_Unbounded_Vector
+                    | Type_Unbounded_Array =>
+                     --  The only possibility is vector elements.
+                     pragma Assert (Res_Type.Ulast);
+                     raise Internal_Error;
+                  when others =>
+                     raise Internal_Error;
+               end case;
             end;
          when Type_Vector
            | Type_Array =>