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* elab-vhdl_annotations(annotate_interface_list_subtype): adjustTristan Gingold2023-01-121-3/+15
| | | | Checking is_ref is not enough because of instantiation
* testsuite/gna: add a test for #2303Tristan Gingold2023-01-122-0/+19
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* simul: fix handling of drivers/sensitivity within processesTristan Gingold2023-01-123-21/+25
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* synth: fix handle of protected type bodies within instantiated packages.Tristan Gingold2023-01-123-3/+30
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* elab-vhdl_types: improve handling of record subtypesTristan Gingold2023-01-122-18/+27
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* ghdl_simul: add commands to use libghdlTristan Gingold2023-01-121-0/+2
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* synth: handle operator as conversion functionTristan Gingold2023-01-121-1/+13
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* vhdl-sem_names: finish prefix of element attribute namesTristan Gingold2023-01-121-22/+32
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* testsuite/gna: adjust harness for #1257Tristan Gingold2023-01-121-2/+2
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* synth: report values in bound errorsTristan Gingold2023-01-122-9/+40
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* testsuite/gna: adjust harness for #1125Tristan Gingold2023-01-121-1/+1
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* synth: use same wording for direction mismatch as simulationTristan Gingold2023-01-121-1/+2
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* Dependency Graphs (#2308)Patrick Lehmann2023-01-1234-338/+698
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * Further fixes to the example code. * Bumped dependencies. * Fixed Debouncer example code. * Some more cleanup. * Black's opinion. * Run with pyVHDLModel dev-branch. * Fixed imports for Name. * Fixed test case. * Added a formatter to write dependency graphs and hierarchy as graphml. * Improved GraphML formatting. * Write compile order graph. * Computing compile order. * Bumped dependencies. * Black's opinion. * Fixed incorrect dependency.
* testsuite/gna: add a test for #2307Tristan Gingold2023-01-112-0/+21
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* synth-vhdl_eval: handle to_X01 for bit to std_ulogic.Tristan Gingold2023-01-113-0/+39
| | | | Fix #2307
* synth: handle entity attributesTristan Gingold2023-01-111-2/+18
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* synth: handle universal r*i and i*r mul, physical mod.Tristan Gingold2023-01-111-1/+9
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* synth: handle element attributeTristan Gingold2023-01-114-9/+39
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* synth: fix matching comparaison tablesTristan Gingold2023-01-111-27/+27
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* synth: rework error handling in file operationsTristan Gingold2023-01-113-43/+63
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* simul: avoid a crash after an error in a conditionTristan Gingold2023-01-111-1/+6
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* synth: improve support of PSL endpointsTristan Gingold2023-01-114-4/+8
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* synth: avoid a crash on very large object typesTristan Gingold2023-01-111-0/+3
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* synth: check float ranges in subtype conversionTristan Gingold2023-01-113-2/+25
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* simul: allow function calls in signal association by valueTristan Gingold2023-01-111-0/+2
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* synth: add a check for v87 concatenationsTristan Gingold2023-01-111-1/+6
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* synth: support constant declarations in protected typesTristan Gingold2023-01-111-0/+1
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* vhdl-configuration: relax top-level unit restrictionsTristan Gingold2023-01-111-4/+5
| | | | Allow generics without default values if the type is fully constrained
* synth: handle file subtypeTristan Gingold2023-01-112-1/+9
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* simul: improve support of psl in debuggerTristan Gingold2023-01-112-4/+13
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* simul: handle psl assume directivesTristan Gingold2023-01-111-0/+2
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* simul: add sensitivity for psl processesTristan Gingold2023-01-111-4/+7
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* synth: allow file declaration in protected objectsTristan Gingold2023-01-111-1/+2
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* elab-vhdl_files: remove incorrect assertionTristan Gingold2023-01-111-1/+0
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* simul: improve assertion messages for pslTristan Gingold2023-01-112-28/+45
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* synth: avoid a crash after error on signal associationTristan Gingold2023-01-111-2/+6
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* simul: add debug command 'run -s'Tristan Gingold2023-01-113-8/+18
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* simul: handle array element resolutionTristan Gingold2023-01-111-1/+6
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* synth: also elaborate dependencies of configurationsTristan Gingold2023-01-111-0/+4
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* simul: improve debugger outputTristan Gingold2023-01-111-5/+5
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* simul: handle -gGEN=VAL options after the unitTristan Gingold2023-01-111-7/+41
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* synth: fix memory allocation in predefined function callsTristan Gingold2023-01-103-1/+8
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* synth: adjust unshare_type for unbounded composite typesTristan Gingold2023-01-101-4/+14
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* synth: check rem/mod by 0Tristan Gingold2023-01-101-2/+14
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* testsuite/synth: adjust code for #1926Tristan Gingold2023-01-101-8/+8
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* simul: enable all debug features during elaborationTristan Gingold2023-01-102-5/+3
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* synth: handle indexes in arrays conversionTristan Gingold2023-01-105-17/+85
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* vhdl-sem_inst: adjust instantiation of interface typeTristan Gingold2023-01-101-0/+3
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* synth: add comments, minor rewriteTristan Gingold2023-01-103-6/+10
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* vhdl-sem_inst: fix build of suspend state chainTristan Gingold2023-01-101-1/+1
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