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| author | Tristan Gingold <tgingold@free.fr> | 2023-01-11 07:01:21 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2023-01-11 07:01:21 +0100 |
| commit | 291a8d4048e513270312afe5d7c3ca930f634724 (patch) | |
| tree | 980323cefeac0453ef0eecc7e98089ddc13f4888 | |
| parent | e7dba34e2b1f38f920cef3c4faed449921200668 (diff) | |
| download | ghdl-291a8d4048e513270312afe5d7c3ca930f634724.tar.gz ghdl-291a8d4048e513270312afe5d7c3ca930f634724.tar.bz2 ghdl-291a8d4048e513270312afe5d7c3ca930f634724.zip | |
simul: avoid a crash after an error in a condition
| -rw-r--r-- | src/simul/simul-vhdl_simul.adb | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/src/simul/simul-vhdl_simul.adb b/src/simul/simul-vhdl_simul.adb index 989ae0e30..cc68914ea 100644 --- a/src/simul/simul-vhdl_simul.adb +++ b/src/simul/simul-vhdl_simul.adb @@ -575,7 +575,12 @@ package body Simul.Vhdl_Simul is Mark_Expr_Pool (Mark); Cond_Val := Synth.Vhdl_Expr.Synth_Expression (Inst, Cond); - Res := Read_Discrete (Cond_Val) = 1; + if Cond_Val /= No_Valtyp then + Res := Read_Discrete (Cond_Val) = 1; + else + -- What could we do ? + Res := False; + end if; Release_Expr_Pool (Mark); return Res; |