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| author | Tristan Gingold <tgingold@free.fr> | 2023-01-11 05:14:39 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2023-01-11 05:14:39 +0100 |
| commit | 447d8371225b84145723ecb78461b8935f3216a0 (patch) | |
| tree | 109de0f26b538fe3ee02e43616f581f5d030e4be | |
| parent | d7ce45a42f681d063373b75dd4fb5118e13de1c0 (diff) | |
| download | ghdl-447d8371225b84145723ecb78461b8935f3216a0.tar.gz ghdl-447d8371225b84145723ecb78461b8935f3216a0.tar.bz2 ghdl-447d8371225b84145723ecb78461b8935f3216a0.zip | |
simul: improve assertion messages for psl
| -rw-r--r-- | src/simul/simul-vhdl_simul.adb | 20 | ||||
| -rw-r--r-- | src/synth/synth-vhdl_stmts.adb | 53 |
2 files changed, 45 insertions, 28 deletions
diff --git a/src/simul/simul-vhdl_simul.adb b/src/simul/simul-vhdl_simul.adb index 2a330d472..54423a009 100644 --- a/src/simul/simul-vhdl_simul.adb +++ b/src/simul/simul-vhdl_simul.adb @@ -1391,11 +1391,21 @@ package body Simul.Vhdl_Simul is Diag_C (":@"); Diag_C_Now; Diag_C (":("); - if Get_Kind (Stmt) = Iir_Kind_Report_Statement then - Diag_C ("report"); - else - Diag_C ("assert"); - end if; + case Get_Kind (Stmt) is + when Iir_Kind_Report_Statement => + Diag_C ("report"); + when Iir_Kind_Assertion_Statement + | Iir_Kind_Concurrent_Assertion_Statement => + Diag_C ("assert"); + when Iir_Kind_Psl_Assert_Directive => + Diag_C ("psl assertion"); + when Iir_Kind_Psl_Assume_Directive => + Diag_C ("psl assumption"); + when Iir_Kind_Psl_Cover_Directive => + Diag_C ("psl cover"); + when others => + raise Types.Internal_Error; + end case; Diag_C (' '); case Severity is when Note_Severity => diff --git a/src/synth/synth-vhdl_stmts.adb b/src/synth/synth-vhdl_stmts.adb index 6a9d0a348..969a70227 100644 --- a/src/synth/synth-vhdl_stmts.adb +++ b/src/synth/synth-vhdl_stmts.adb @@ -3408,7 +3408,7 @@ package body Synth.Vhdl_Stmts is is use Simple_IO; Rep_Expr : constant Node := Get_Report_Expression (Stmt); - Sev_Expr : constant Node := Get_Severity_Expression (Stmt); + Sev_Expr : Node; Marker : Mark_Type; Rep : Valtyp; Sev : Valtyp; @@ -3425,31 +3425,38 @@ package body Synth.Vhdl_Stmts is end if; Strip_Const (Rep); end if; - if Sev_Expr /= Null_Node then - Sev := Synth_Expression (Syn_Inst, Sev_Expr); - if Sev = No_Valtyp then - Set_Error (Syn_Inst); - Release_Expr_Pool (Marker); - return; + + if Get_Kind (Stmt) /= Iir_Kind_Psl_Cover_Directive then + Sev_Expr := Get_Severity_Expression (Stmt); + + if Sev_Expr /= Null_Node then + Sev := Synth_Expression (Syn_Inst, Sev_Expr); + if Sev = No_Valtyp then + Set_Error (Syn_Inst); + Release_Expr_Pool (Marker); + return; + end if; + Strip_Const (Sev); end if; - Strip_Const (Sev); - end if; - if Sev = No_Valtyp then - case Get_Kind (Stmt) is - when Iir_Kind_Report_Statement - | Iir_Kind_Psl_Cover_Directive => - Sev_V := Note_Severity; - when Iir_Kind_Assertion_Statement - | Iir_Kind_Concurrent_Assertion_Statement - | Iir_Kind_Psl_Assert_Directive - | Iir_Kind_Psl_Assume_Directive => - Sev_V := Error_Severity; - when others => - raise Internal_Error; - end case; + if Sev = No_Valtyp then + case Get_Kind (Stmt) is + when Iir_Kind_Report_Statement + | Iir_Kind_Psl_Cover_Directive => + Sev_V := Note_Severity; + when Iir_Kind_Assertion_Statement + | Iir_Kind_Concurrent_Assertion_Statement + | Iir_Kind_Psl_Assert_Directive + | Iir_Kind_Psl_Assume_Directive => + Sev_V := Error_Severity; + when others => + raise Internal_Error; + end case; + else + Sev_V := Natural (Read_Discrete (Sev)); + end if; else - Sev_V := Natural (Read_Discrete (Sev)); + Sev_V := Note_Severity; end if; if Assertion_Report_Handler /= null then |