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| author | Tristan Gingold <tgingold@free.fr> | 2019-12-05 22:35:16 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-12-05 22:35:16 +0100 |
| commit | 8eea89ff1969a28e2360c7240a1f9c37326d8fa5 (patch) | |
| tree | 9cafff02cf83ea30139132b5a05eb2a81efc0a28 | |
| parent | 7491d9ff10c9ae17d917832d9e1b25a84af94e06 (diff) | |
| download | ghdl-8eea89ff1969a28e2360c7240a1f9c37326d8fa5.tar.gz ghdl-8eea89ff1969a28e2360c7240a1f9c37326d8fa5.tar.bz2 ghdl-8eea89ff1969a28e2360c7240a1f9c37326d8fa5.zip | |
netlists-disp_vhdl: handle 1-bit add/sub.
| -rw-r--r-- | src/synth/netlists-disp_vhdl.adb | 16 |
1 files changed, 12 insertions, 4 deletions
diff --git a/src/synth/netlists-disp_vhdl.adb b/src/synth/netlists-disp_vhdl.adb index 763a08f29..c063c7425 100644 --- a/src/synth/netlists-disp_vhdl.adb +++ b/src/synth/netlists-disp_vhdl.adb @@ -902,11 +902,19 @@ package body Netlists.Disp_Vhdl is Disp_X_Lit (Get_Width (Get_Output (Inst, 0))); Put_Line (" when others;"); when Id_Add => - Disp_Template (" \o0 <= std_logic_vector (\ui0 + \ui1);" & NL, - Inst); + if Get_Width (Get_Output (Inst, 0)) = 1 then + Disp_Template (" \o0 <= \i0 xor \i1; -- add" & NL, Inst); + else + Disp_Template (" \o0 <= std_logic_vector (\ui0 + \ui1);" & NL, + Inst); + end if; when Id_Sub => - Disp_Template (" \o0 <= std_logic_vector (\ui0 - \ui1);" & NL, - Inst); + if Get_Width (Get_Output (Inst, 0)) = 1 then + Disp_Template (" \o0 <= \i0 xor \i1; -- sub" & NL, Inst); + else + Disp_Template (" \o0 <= std_logic_vector (\ui0 - \ui1);" & NL, + Inst); + end if; when Id_Umul => Disp_Template (" \o0 <= std_logic_vector (resize (\ui0 * \ui1, \n0));" & NL, |