testsuite/vets/vhdl-ams: fix syntax.

14 files changed, 42 insertions, 42 deletions

diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/analog_models/static_cmos_inv_ramp.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/analog_models/static_cmos_inv_ramp.ams
index 5aeb07ba0..7ab084991 100644
--- a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/analog_models/static_cmos_inv_ramp.ams
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/analog_models/static_cmos_inv_ramp.ams
@@ -40,7 +40,7 @@
 
 
 PACKAGE electricalSystem IS
-    NATURE electrical IS real ACROSS real THROUGH;
+    NATURE electrical IS real ACROSS real THROUGH ground reference;
     FUNCTION POW(X,Y: real) RETURN real;
     FUNCTION SIN(X : real) RETURN real;
     FUNCTION EXP(X : real) RETURN real;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/break_stmt/test123.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/break_stmt/test123.ams
index 9d3e53e7b..9f94606c9 100644
--- a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/break_stmt/test123.ams
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/break_stmt/test123.ams
@@ -49,7 +49,7 @@
 -- +g and -g.
 ----------------------------------------------------------------------
 PACKAGE electricalSystem IS
-    NATURE electrical IS real ACROSS real THROUGH;
+    NATURE electrical IS real ACROSS real THROUGH ground reference;
     FUNCTION SIN(X : real) RETURN real;
 --    alias ground is electrical'reference;
 END PACKAGE electricalSystem;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/break_stmt/test134.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/break_stmt/test134.ams
index 0f80d28c0..24e568282 100644
--- a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/break_stmt/test134.ams
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/break_stmt/test134.ams
@@ -54,7 +54,7 @@
 ---------------------------------------------------------------------------------
 PACKAGE electricalSystem IS
     SUBTYPE voltage is real;
-    NATURE electrical IS real ACROSS real THROUGH;
+    NATURE electrical IS real ACROSS real THROUGH ground reference;
     FUNCTION SIN(X : real) RETURN real;
     FUNCTION EXP(X : real) RETURN real;
     FUNCTION SQRT(X : real) RETURN real;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/break_stmt/test180.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/break_stmt/test180.ams
index 3e33069e4..7a0e136b8 100644
--- a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/break_stmt/test180.ams
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/break_stmt/test180.ams
@@ -49,7 +49,7 @@
 -- codition.
 
 PACKAGE electricalSystem IS
-    NATURE electrical IS real ACROSS real THROUGH; -- GROUND REFERENCE;
+    NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE;
     FUNCTION SIN(X : real) RETURN real;
     FUNCTION EXP(X : real) RETURN real;
 END PACKAGE electricalSystem;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/break_stmt/test181.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/break_stmt/test181.ams
index 4c7caf467..f8840367f 100644
--- a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/break_stmt/test181.ams
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/break_stmt/test181.ams
@@ -49,7 +49,7 @@
 -- codition.
 
 PACKAGE electricalSystem IS
-    NATURE electrical IS real ACROSS real THROUGH; -- GROUND REFERENCE;
+    NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE;
     FUNCTION SIN(X : real) RETURN real;
     FUNCTION EXP(X : real) RETURN real;
 END PACKAGE electricalSystem;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/above_attr.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/above_attr.ams
index c3bf7abd0..1d3f0c689 100644
--- a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/above_attr.ams
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/above_attr.ams
@@ -65,7 +65,7 @@ ABSIG<=V1'above(V2+1.0);
             
  testbench:PROCESS
         VARIABLE outline : LINE;
-        VARIABLE Headline   : string(1 TO 33) :=
+        VARIABLE Headline   : string(1 TO 10) :=
             "time ABSIG";
         VARIABLE   seperator    : string(1 TO 1) := " ";
         VARIABLE   flag     : bit := '0';
@@ -77,7 +77,7 @@ ABSIG<=V1'above(V2+1.0);
             WRITE(outline,Headline);
             WRITELINE(outfile,outline);
         ELSE
-            WRITE(outline, now);
+            WRITE(outline, time'(now));
             WRITE(outline,seperator);
             IF (ABSIG = true) THEN
             tmp:='1';
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/generic_model.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/generic_model.ams
index eb636b540..e0427eb5c 100644
--- a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/generic_model.ams
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/generic_model.ams
@@ -112,7 +112,7 @@ BEGIN
 
  testbench:PROCESS
         VARIABLE outline : LINE;
-        VARIABLE Headline   : string(1 TO 8) :=
+        VARIABLE Headline   : string(1 TO 7) :=
             "time y ";
         VARIABLE   seperator    : string(1 TO 1) := " ";
         VARIABLE   flag     : bit := '0';
@@ -123,7 +123,7 @@ BEGIN
             WRITE(outline,Headline);
             WRITELINE(outfile,outline);
         ELSE
-            WRITE(outline, now);
+            WRITE(outline, time'(now));
             WRITE(outline,seperator);
             WRITE(outline,y);
             WRITE(outline,seperator);
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/mixed_model_1.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/mixed_model_1.ams
index 10fd3bbeb..c2be9b915 100644
--- a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/mixed_model_1.ams
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/mixed_model_1.ams
@@ -61,7 +61,7 @@ end process;
 
  testbench:PROCESS
         VARIABLE outline : LINE;
-        VARIABLE Headline   : string(1 TO 8) :=
+        VARIABLE Headline   : string(1 TO 6) :=
             "time y";
         VARIABLE   seperator    : string(1 TO 1) := " ";
         VARIABLE   flag     : bit := '0';
@@ -72,7 +72,7 @@ end process;
             WRITE(outline,Headline);
             WRITELINE(outfile,outline);
         ELSE
-            WRITE(outline, now);
+            WRITE(outline, time'(now));
             WRITE(outline,seperator);
             WRITE(outline,y);
             WRITE(outline,seperator);
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/mixed_model_2.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/mixed_model_2.ams
index dd80c233e..89b3a0100 100644
--- a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/mixed_model_2.ams
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/mixed_model_2.ams
@@ -111,7 +111,7 @@ BEGIN
 
  testbench:PROCESS
         VARIABLE outline : LINE;
-        VARIABLE Headline   : string(1 TO 8) :=
+        VARIABLE Headline   : string(1 TO 6) :=
             "time y";
         VARIABLE   seperator    : string(1 TO 1) := " ";
         VARIABLE   flag     : bit := '0';
@@ -122,7 +122,7 @@ BEGIN
             WRITE(outline,Headline);
             WRITELINE(outfile,outline);
         ELSE
-            WRITE(outline, now);
+            WRITE(outline, time'(now));
             WRITE(outline,seperator);
             WRITE(outline,y);
             WRITE(outline,seperator);
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/mixed_tests/mixed_1.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/mixed_tests/mixed_1.ams
index 37cd1280c..6cfd199a6 100644
--- a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/mixed_tests/mixed_1.ams
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/mixed_tests/mixed_1.ams
@@ -77,7 +77,7 @@ BEGIN
 
 testbench:PROCESS(y)
     VARIABLE outline : LINE;
-    VARIABLE Headline   : string(1 TO 52) :=
+    VARIABLE Headline   : string(1 TO 7) :=
       "time  y";
     VARIABLE   seperator    : string(1 TO 1) := " ";
     VARIABLE   flag     : bit := '0';
@@ -88,7 +88,7 @@ testbench:PROCESS(y)
       WRITE(outline,Headline);
       WRITELINE(outfile,outline);
     ELSE
-      WRITE(outline, now);
+      WRITE(outline, time'(now));
       WRITE(outline,seperator);  
       WRITE(outline, y);
       WRITE(outline, seperator);
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/mixed_tests/mixed_2.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/mixed_tests/mixed_2.ams
index c78005790..16bb65d58 100644
--- a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/mixed_tests/mixed_2.ams
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/mixed_tests/mixed_2.ams
@@ -76,7 +76,7 @@ BEGIN
 
 testbench:PROCESS(y,x)
     VARIABLE outline : LINE;
-    VARIABLE Headline   : string(1 TO 52) :=
+    VARIABLE Headline   : string(1 TO 9) :=
       "time  y x";
     VARIABLE   seperator    : string(1 TO 1) := " ";
     VARIABLE   flag     : bit := '0';
@@ -87,7 +87,7 @@ testbench:PROCESS(y,x)
       WRITE(outline,Headline);
       WRITELINE(outfile,outline);
     ELSE
-      WRITE(outline, now);
+      WRITE(outline, time'(now));
       WRITE(outline,seperator);  
       WRITE(outline, y);
       WRITE(outline, seperator);
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS1_Mixed_Sig/tb_CS1.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS1_Mixed_Sig/tb_CS1.vhd
index f18d88bed..a1e86336e 100644
--- a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS1_Mixed_Sig/tb_CS1.vhd
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS1_Mixed_Sig/tb_CS1.vhd
@@ -161,14 +161,14 @@ begin
     -- Component instances
     XCMP1 : entity work.clock(ideal)
         generic map(
-            period => 10us
+            period => 10 us
         )
         port map(
             CLK_OUT => clk_100k
         );
     XCMP2 : entity work.clock(ideal)
         generic map(
-            period => 150us
+            period => 150 us
         )
         port map(
             CLK_OUT => clk_6K
@@ -1503,7 +1503,7 @@ begin
         );
     clk_en_rudder : entity work.clock_en(ideal)
         generic map(
-            pw => 500ns
+            pw => 500 ns
         )
         port map(
             CLOCK_OUT => XSIG010008,
@@ -1511,7 +1511,7 @@ begin
         );
     XCMP5 : entity work.inverter(ideal)
         generic map(
-            delay => 2us
+            delay => 2 us
         )
         port map(
             input => XSIG010022,
@@ -1519,7 +1519,7 @@ begin
         );
     XCMP8 : entity work.inverter(ideal)
         generic map(
-            delay => 2us
+            delay => 2 us
         )
         port map(
             input => XSIG010020,
@@ -1527,7 +1527,7 @@ begin
         );
     XCMP9 : entity work.inverter(ideal)
         generic map(
-            delay => 2us
+            delay => 2 us
         )
         port map(
             input => XSIG010022,
@@ -2455,4 +2455,4 @@ begin
             ch1_pw => throttle_servo
         );
 end TB_CS1;
---
\ No newline at end of file
+--
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS5_RC_Airplane/tb_CS5_Amp_Lim.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS5_RC_Airplane/tb_CS5_Amp_Lim.vhd
index 41fedb4a0..7d90c9b79 100644
--- a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS5_RC_Airplane/tb_CS5_Amp_Lim.vhd
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS5_RC_Airplane/tb_CS5_Amp_Lim.vhd
@@ -233,7 +233,7 @@ end rudder_servo;
 -- File       : gear_rv_r.vhd
 -- Author     : Mentor Graphics
 -- Created    : 2001/10/10
--- Last update: 2002/05/21
+-- Last update: 2019-12-30
 -------------------------------------------------------------------------------
 -- Description: Gear Model (ROTATIONAL_V/ROTATIONAL domains)
 -------------------------------------------------------------------------------
@@ -743,9 +743,9 @@ entity v_pulse is
   generic (
     initial  : voltage := 0.0;          -- initial value [Volts]
     pulse    : voltage;                 -- pulsed value [Volts]
-    ti2p     : time    := 1ns;          -- initial to pulse [Sec]
-    tp2i     : time    := 1ns;          -- pulse to initial [Sec]
-    delay    : time    := 0ms;          -- delay time [Sec]
+    ti2p     : time    := 1 ns;          -- initial to pulse [Sec]
+    tp2i     : time    := 1 ns;          -- pulse to initial [Sec]
+    delay    : time    := 0 ms;          -- delay time [Sec]
     width    : time;                    -- duration of pulse [Sec]
     period   : time;                    -- period [Sec]
     ac_mag   : voltage := 1.0;          -- AC magnitude [Volts]
@@ -1062,11 +1062,11 @@ begin
         generic map(
             initial => 0.0,
             pulse => 4.8,
-            ti2p => 300ms,
-            tp2i => 300ms,
-            delay => 100ms,
-            width => 5ms,
-            period => 605ms
+            ti2p => 300 ms,
+            tp2i => 300 ms,
+            delay => 100 ms,
+            width => 5 ms,
+            period => 605 ms
         )
         port map(
             pos => src_in,
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS5_RC_Airplane/tb_CS5_CC_Rudder.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS5_RC_Airplane/tb_CS5_CC_Rudder.vhd
index 60fdc24be..352b3a500 100644
--- a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS5_RC_Airplane/tb_CS5_CC_Rudder.vhd
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS5_RC_Airplane/tb_CS5_CC_Rudder.vhd
@@ -234,7 +234,7 @@ end rudder_servo;
 -- File       : gear_rv_r.vhd
 -- Author     : Mentor Graphics
 -- Created    : 2001/10/10
--- Last update: 2002/05/21
+-- Last update: 2019-12-30
 -------------------------------------------------------------------------------
 -- Description: Gear Model (ROTATIONAL_V/ROTATIONAL domains)
 -------------------------------------------------------------------------------
@@ -563,7 +563,7 @@ use IEEE_proposed.electrical_systems.all;
 use IEEE_proposed.mechanical_systems.all;
 
 entity RF_xmtr_rcvr is
-generic (td : time := 0ns);
+generic (td : time := 0 ns);
 port
 (
       tdm_in : in std_logic ;
@@ -734,14 +734,14 @@ begin
     -- Component instances
     XCMP1 : entity work.clock(ideal)
         generic map(
-            period => 10us
+            period => 10 us
         )
         port map(
             CLK_OUT => clk_100k
         );
     XCMP2 : entity work.clock(ideal)
         generic map(
-            period => 150us
+            period => 150 us
         )
         port map(
             CLK_OUT => clk_6K
@@ -2180,7 +2180,7 @@ begin
         );
     clk_en_rudder : entity work.clock_en(ideal)
         generic map(
-            pw => 500ns
+            pw => 500 ns
         )
         port map(
             CLOCK_OUT => XSIG010008,
@@ -2188,7 +2188,7 @@ begin
         );
     XCMP5 : entity work.inverter(ideal)
         generic map(
-            delay => 2us
+            delay => 2 us
         )
         port map(
             input => XSIG010022,
@@ -2196,7 +2196,7 @@ begin
         );
     XCMP8 : entity work.inverter(ideal)
         generic map(
-            delay => 2us
+            delay => 2 us
         )
         port map(
             input => XSIG010020,
@@ -2204,7 +2204,7 @@ begin
         );
     XCMP9 : entity work.inverter(ideal)
         generic map(
-            delay => 2us
+            delay => 2 us
         )
         port map(
             input => XSIG010022,
@@ -3461,7 +3461,7 @@ begin
         );
     clock1 : entity work.clock(ideal)
         generic map(
-            period => 9.375us
+            period => 9.375 us
         )
         port map(
             CLK_OUT => clk16x