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* synth: renaming (synth-static_proc -> synth-vhdl_static_proc)Tristan Gingold2021-04-163-6/+6
* synth: refactoring (synth.files_operations -> synth.vhdl_files)Tristan Gingold2021-04-166-11/+11
* synth: renaming (synth.oper -> synth.vhdl_oper)Tristan Gingold2021-04-164-11/+11
* synth: refactoring (synth.aggr -> synth.vhdl_aggr)Tristan Gingold2021-04-163-7/+7
* synth: rename synth-context to synth-vhdl_contextTristan Gingold2021-04-1616-25/+25
* testsuite/gna: add a test for #1724Tristan Gingold2021-04-152-0/+11
* vhdl: also allow type and subtype declarations in vunit. For #1724Tristan Gingold2021-04-152-0/+4
* testsuite/synth: add a test for previous commitTristan Gingold2021-04-152-0/+72
* synth: avoid crash in case of non-elaboratable generic.Tristan Gingold2021-04-152-4/+10
* vhdl-canon_psl: handle imp_boolTristan Gingold2021-04-151-2/+3
* testsuite/gna: add test for #1724Tristan Gingold2021-04-153-0/+33
* vhdl: handle constant declarations in PSL vunit. Fix #1724Tristan Gingold2021-04-152-0/+2
* testsuite/gna: add tests for #1721Tristan Gingold2021-04-133-0/+43
* testsuite/gna: add a test for #1721Tristan Gingold2021-04-132-0/+22
* trans-chap9: handle N_Imp_Bool for PSL. For #1721Tristan Gingold2021-04-131-0/+21
* testsuite/gna: add a test for #1721Tristan Gingold2021-04-132-0/+29
* psl: suffix implication are properties (for simple subset). For #1721Tristan Gingold2021-04-133-6/+5
* testsuite/gna: add a test for #1721Tristan Gingold2021-04-133-0/+80
* vhdl-sem_psl.adb: can also extract clock from SERE. For #1721Tristan Gingold2021-04-131-1/+5
* testsuite/gna: add a test for #1717Tristan Gingold2021-04-112-0/+60
* vhdl-sem_names.adb: fix check for object prefix of subtype attribute. Fix #1717Tristan Gingold2021-04-111-3/+1
* src: Clarify error for conditional signal assignment.Ondrej Ille2021-04-111-1/+2
* src: Allow case generate only in VHDL 2008.Ondrej Ille2021-04-111-0/+1
* src: Unify check for VHDL at least 2008Ondrej Ille2021-04-111-47/+25
* trans-chap9.adb: fix out of scope reference.Tristan Gingold2021-04-101-2/+3
* testsuite/gna: add a test for #1718Tristan Gingold2021-04-102-0/+20
* ghdldrv,configure: allow LIB.UNIT name for -e/-r commands. Fix #1718Tristan Gingold2021-04-108-38/+129
* src/grt: Avhpi - Specify enum numbers as in VHDL LRM. Add 2008 version enumer...Ondrej Ille2021-04-081-5/+483
* testsuite: Adjust regression for new format of PSL report.Ondrej Ille2021-04-082-6/+12
* src: Fix PSL start count assignment for PSL endpoints.Ondrej Ille2021-04-081-9/+9
* src: Introduce two separate PSL counters (Finish and Start).Ondrej Ille2021-04-085-19/+57
* src: Adjust grt-psl to use PSL RTI type.Ondrej Ille2021-04-081-5/+5
* src: Adjust disp-rti for new PSL RTI type.Ondrej Ille2021-04-081-12/+27
* src: grt-utils. Fix path look-up fo PSL RTis since they now have Parent.Ondrej Ille2021-04-082-8/+7
* src: Define PSL type RTI with simplified assertion state.Ondrej Ille2021-04-085-6/+110
* grt: Dont build path for PSL RTIs. They dont have parents, therefore Get_Path...Ondrej Ille2021-04-081-0/+12
* testsuite/gna: add a test for #1715Tristan Gingold2021-04-073-0/+80
* vhdl-sem_decls.adb: handle both anonymous signal and signal attribute. Fix #...Tristan Gingold2021-04-071-0/+2
* testsuite: Adjust regression for caret-diagnostics on by default.Ondrej Ille2021-04-053-0/+14
* src: Set fcaret-diagnostics to be on by default. Clean unused Warn_Undriven.Ondrej Ille2021-04-051-4/+1
* src: Remove obsolete FIXME, file_open_information parsed. Default "IN"/"READ_...Ondrej Ille2021-04-051-1/+0
* testsuite.py: set exit statusTristan Gingold2021-04-051-1/+5
* ghdlsynth.adb: fix a previous commitTristan Gingold2021-04-051-1/+1
* testsuite/gna: add more tests for #1708Tristan Gingold2021-04-056-0/+176
* vhdl-sem_psl.adb: handle goto/equal repeated sequence. For #1708Tristan Gingold2021-04-051-8/+20
* vhdl-parse_psl.adb: handle parenthesis boolean prefixes. For #1708Tristan Gingold2021-04-051-29/+62
* vhdl and libraries: add support for binding to a foreign moduleTristan Gingold2021-04-057-124/+237
* ghdldrv/: initial support for foreign modulesTristan Gingold2021-04-055-11/+28
* vhdl: add Iir_Kind_Foreign_ModuleTristan Gingold2021-04-0511-631/+757
* pnodes.py: fix a typoTristan Gingold2021-04-051-1/+1
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