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author | Tristan Gingold <tgingold@free.fr> | 2021-04-13 19:43:37 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2021-04-13 19:43:37 +0200 |
commit | b6091b3eae56aa8eb61252fa97a00a8a29562e0f (patch) | |
tree | de8320d646e865ea1ed830156ebc2ee60ab0041b | |
parent | d6a8f93b543ede48005000d90612060ef05cfd8c (diff) | |
download | ghdl-b6091b3eae56aa8eb61252fa97a00a8a29562e0f.tar.gz ghdl-b6091b3eae56aa8eb61252fa97a00a8a29562e0f.tar.bz2 ghdl-b6091b3eae56aa8eb61252fa97a00a8a29562e0f.zip |
vhdl-sem_psl.adb: can also extract clock from SERE. For #1721
-rw-r--r-- | src/vhdl/vhdl-sem_psl.adb | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/src/vhdl/vhdl-sem_psl.adb b/src/vhdl/vhdl-sem_psl.adb index 18141eeb8..025647e94 100644 --- a/src/vhdl/vhdl-sem_psl.adb +++ b/src/vhdl/vhdl-sem_psl.adb @@ -502,7 +502,8 @@ package body Vhdl.Sem_Psl is Res : PSL_Node; begin case Get_Kind (Prop) is - when N_Braced_SERE => + when N_Braced_SERE + | N_Clocked_SERE => return Sem_Sequence (Prop); when N_Star_Repeat_Seq | N_Plus_Repeat_Seq => @@ -659,6 +660,9 @@ package body Vhdl.Sem_Psl is if Get_Kind (Child) = N_Clock_Event then Set_Property (Prop, Get_Property (Child)); Clk := Get_Boolean (Child); + elsif Get_Kind (Child) = N_Clocked_SERE then + Clk := Get_Boolean (Child); + Set_Property (Prop, Get_SERE (Child)); end if; when N_Property_Instance => Child := Get_Declaration (Prop); |