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authorTristan Gingold <tgingold@free.fr>2021-04-13 21:01:04 +0200
committerTristan Gingold <tgingold@free.fr>2021-04-13 21:01:04 +0200
commit015c416c33fb1aaee8c744e15229cd6762043474 (patch)
treeec197592a74254bbb10fb9b18dc4b4e63a6a341a
parent916cadd8aa94741e770f28f9f09fe1f9b61062ea (diff)
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testsuite/gna: add a test for #1721
-rwxr-xr-xtestsuite/gna/issue1721/testsuite.sh3
-rw-r--r--testsuite/gna/issue1721/top3.vhdl19
2 files changed, 22 insertions, 0 deletions
diff --git a/testsuite/gna/issue1721/testsuite.sh b/testsuite/gna/issue1721/testsuite.sh
index e4a6e56cc..f3245dd6b 100755
--- a/testsuite/gna/issue1721/testsuite.sh
+++ b/testsuite/gna/issue1721/testsuite.sh
@@ -9,6 +9,9 @@ elab_simulate top1
analyze_failure top2.vhdl
+analyze top3.vhdl
+elab_simulate top3
+
clean
echo "Test successful"
diff --git a/testsuite/gna/issue1721/top3.vhdl b/testsuite/gna/issue1721/top3.vhdl
new file mode 100644
index 000000000..52522c7b7
--- /dev/null
+++ b/testsuite/gna/issue1721/top3.vhdl
@@ -0,0 +1,19 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity top3 is
+end entity;
+
+architecture a of top3 is
+ signal a,b,c,d : std_logic := '0';
+ signal clk_sys, clk1, clk2 : std_logic;
+begin
+ -- psl default clock is clk_sys;
+
+ -- Following error is thrown: "translate_psl_expr: cannot handle N_IMP_BOOL"
+ -- Combination of "never" + implication is not very usefull, since
+ -- implication is always true apart from case where 1 -> 0, therefore it
+ -- will mostly fail, however, it should not crash tool (the same goes for
+ -- previous case too)
+ -- psl my_seq : assert never (a -> b);
+end;