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* netlists: add 2 flags per instance, including a mark flag.Tristan Gingold2019-11-112-6/+33
* synth: initial support for file types. For #1004Tristan Gingold2019-11-115-33/+105
* synth: initial support of access type. For #1004Tristan Gingold2019-11-115-4/+76
* Update doc (#1003)1138-4EB2019-11-1136-856/+1011
* synth-decls: handle unassigned signal/object. For issue 65Tristan Gingold2019-11-073-14/+53
* testsuite/synth: add testcase for or short-circuit. #1005Tristan Gingold2019-11-072-3/+28
* synth: also handle or short-circuit. For #1005Tristan Gingold2019-11-071-14/+35
* Makefile.in: adjust libghdl name on windows. For #1010Tristan Gingold2019-11-071-0/+6
* Add testcase for #1011Tristan Gingold2019-11-062-0/+40
* synth: handle record assignment for variables. Fix #1011Tristan Gingold2019-11-061-0/+4
* Add testcase for #1005Tristan Gingold2019-11-062-0/+34
* synth: handle short-circuit and. Fix #1005Tristan Gingold2019-11-061-9/+38
* files_map-editor: add Copy_Source_File.Tristan Gingold2019-11-063-0/+46
* files_map: add Discard_Source_File, Free_Source_File,Tristan Gingold2019-11-063-5/+47
* files_map-editor: turn Replace_Text to a function.Tristan Gingold2019-11-063-30/+39
* vhdl-ieee-std_logic_1164: minor simplification.Tristan Gingold2019-11-061-21/+8
* synth: handle edge operators in synth_predefined_function_call.Tristan Gingold2019-11-064-31/+24
* vhdl: recognize rising_edge/falling_edge.Tristan Gingold2019-11-064-381/+393
* netlists-dump: avoid a crash on unconnected driver.Tristan Gingold2019-11-061-3/+6
* testsuite/synth: add a similar testcase for #1009Tristan Gingold2019-11-062-0/+16
* synth: do not create a value_const of a value_const.Tristan Gingold2019-11-062-1/+6
* Add testcase for #1009Tristan Gingold2019-11-062-0/+25
* synth-expr: do subtype conversion in fill_record_aggregate. Fix #1009Tristan Gingold2019-11-061-1/+2
* Add testcase for #1006Tristan Gingold2019-11-063-0/+46
* synth: unshare default value of variables. Fix #1006Tristan Gingold2019-11-062-4/+42
* netlists-cleanup: do not remove the self-instance.Tristan Gingold2019-11-061-0/+2
* synth-stmts: rewrite target_info to clarify memoryTristan Gingold2019-11-051-18/+56
* synth: do more constant propagation (on build2Tristan Gingold2019-11-054-50/+82
* netlists-disp_vhdl: handle truncate to width 1.Tristan Gingold2019-11-051-2/+7
* netlists-memories: truncate wide addresses.Tristan Gingold2019-11-051-11/+9
* synth-oper: simplify code.Tristan Gingold2019-11-051-7/+4
* netlists: add build2_sresize, simplify code.Tristan Gingold2019-11-053-48/+53
* testsuite/synth: fix permissions.Tristan Gingold2019-11-051-0/+0
* synth: extract netlists-folds from netlists-builders.Tristan Gingold2019-11-0511-160/+216
* netlists-dump: indent output.Tristan Gingold2019-11-053-13/+17
* netlists-memories: adjust message.Tristan Gingold2019-11-051-1/+1
* testsuite/synth: add testcase for #1002.Tristan Gingold2019-11-042-0/+26
* netlists: enable expansion.Tristan Gingold2019-11-041-1/+1
* synth-oper: handle constant not.Tristan Gingold2019-11-041-3/+8
* synth-expr: allow constants in discrete rangeTristan Gingold2019-11-041-0/+2
* testsuite/synth: add a test for previous commit.Tristan Gingold2019-11-043-0/+56
* synth-expr: handle vhdl 2008 aggregates (partially).Tristan Gingold2019-11-042-48/+125
* synth-value: export get_bound_length.Tristan Gingold2019-11-041-0/+3
* ghdlmain: simplify code.Tristan Gingold2019-11-041-4/+1
* vhdl-scanner: handle 'synopsys' pragma.Tristan Gingold2019-11-043-16/+19
* ghdlmain: fix deallocation in response file handling.Tristan Gingold2019-11-041-0/+10
* Add doc of the 3 ways to use PSL with GHDL (Implementation of VHDL -> PSL imp...T. Meissner2019-11-031-15/+84
* netlists-expands: expand rol.Tristan Gingold2019-11-031-0/+30
* synth-oper: use build2_uresizeTristan Gingold2019-11-031-16/+2
* netlists-utils: add clog2Tristan Gingold2019-11-032-0/+8
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