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authorTristan Gingold <tgingold@free.fr>2019-11-06 03:50:01 +0100
committerTristan Gingold <tgingold@free.fr>2019-11-06 03:50:01 +0100
commit08801396bacc680cc150f4bd39bddae7df016aa2 (patch)
tree42adbbbc6bcaa5df5072069a04530103d97e51e3
parent7d82da829488f4cb033ad1ad295f2d86ca9e7e7f (diff)
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Add testcase for #1006
-rw-r--r--testsuite/synth/issue1006/test.vhdl20
-rw-r--r--testsuite/synth/issue1006/test_package.vhdl17
-rwxr-xr-xtestsuite/synth/issue1006/testsuite.sh9
3 files changed, 46 insertions, 0 deletions
diff --git a/testsuite/synth/issue1006/test.vhdl b/testsuite/synth/issue1006/test.vhdl
new file mode 100644
index 000000000..1473d3eb8
--- /dev/null
+++ b/testsuite/synth/issue1006/test.vhdl
@@ -0,0 +1,20 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library work;
+use work.test_package.all;
+
+entity test is
+ generic(
+ MEMORY_SIZE : natural := 4096
+ );
+ port(
+ val_in : in std_logic_vector(63 downto 0)
+ );
+end entity test;
+
+architecture behaviour of test is
+ signal tmp : std_logic_vector(log2(MEMORY_SIZE) - 1 downto 0);
+begin
+ tmp <= val_in(log2(MEMORY_SIZE) - 1 downto 0);
+end architecture behaviour;
diff --git a/testsuite/synth/issue1006/test_package.vhdl b/testsuite/synth/issue1006/test_package.vhdl
new file mode 100644
index 000000000..4eeb95fa5
--- /dev/null
+++ b/testsuite/synth/issue1006/test_package.vhdl
@@ -0,0 +1,17 @@
+package test_package is
+ function log2(input : in natural) return natural;
+end package test_package;
+
+package body test_package is
+ function log2(input : in natural) return natural is
+ variable retval : natural := 0;
+ variable temp : natural := input;
+ begin
+ while temp > 1 loop
+ retval := retval + 1;
+ temp := temp / 2;
+ end loop;
+
+ return retval;
+ end function log2;
+end package body test_package;
diff --git a/testsuite/synth/issue1006/testsuite.sh b/testsuite/synth/issue1006/testsuite.sh
new file mode 100755
index 000000000..08fafc2d7
--- /dev/null
+++ b/testsuite/synth/issue1006/testsuite.sh
@@ -0,0 +1,9 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+synth test_package.vhdl test.vhdl -e test > syn_test.vhdl
+analyze test_package.vhdl syn_test.vhdl
+clean
+
+echo "Test successful"