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author | Tristan Gingold <tgingold@free.fr> | 2019-11-06 20:46:06 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-11-06 20:46:06 +0100 |
commit | dedd6c9534c55a09048aa15bffb3e9de2253badd (patch) | |
tree | 135bb132892c23d62cf0d60952989839797c43f0 | |
parent | e4279a1ee9d3c7d4efdbd0c195a122a9100e7027 (diff) | |
download | ghdl-dedd6c9534c55a09048aa15bffb3e9de2253badd.tar.gz ghdl-dedd6c9534c55a09048aa15bffb3e9de2253badd.tar.bz2 ghdl-dedd6c9534c55a09048aa15bffb3e9de2253badd.zip |
Add testcase for #1005
-rw-r--r-- | testsuite/synth/issue1005/test.vhdl | 22 | ||||
-rwxr-xr-x | testsuite/synth/issue1005/testsuite.sh | 12 |
2 files changed, 34 insertions, 0 deletions
diff --git a/testsuite/synth/issue1005/test.vhdl b/testsuite/synth/issue1005/test.vhdl new file mode 100644 index 000000000..0388e33f4 --- /dev/null +++ b/testsuite/synth/issue1005/test.vhdl @@ -0,0 +1,22 @@ +library ieee; +use ieee.std_logic_1164.all; +use std.env.stop; + +entity test is + generic ( + SIM : boolean := false + ); + port ( + val : in std_ulogic + ); +end entity test; + +architecture behaviour of test is +begin + process_0: process(all) + begin + if SIM and val = '1' then + stop; + end if; + end process; +end architecture behaviour; diff --git a/testsuite/synth/issue1005/testsuite.sh b/testsuite/synth/issue1005/testsuite.sh new file mode 100755 index 000000000..5643f943a --- /dev/null +++ b/testsuite/synth/issue1005/testsuite.sh @@ -0,0 +1,12 @@ +#! /bin/sh + +. ../../testenv.sh + +GHDL_STD_FLAGS=--std=08 +t=test +synth $t.vhdl -e $t > syn_$t.vhdl +analyze syn_$t.vhdl + +clean + +echo "Test successful" |