iCE40/ghdl - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	vhdl-annotations: annotate procedure call associations	Tristan Gingold	2022-05-25	1	-14/+47
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*	vhdl: move Is_Copyback_Parameter to vhdl-utils	Tristan Gingold	2022-05-25	3	-12/+16
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*	synth: add value_dyn_alias in elab-vhdl_values	Tristan Gingold	2022-05-25	8	-72/+203
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*	elab-vhdl_objtypes: use value_offsets for record elements offset.	Tristan Gingold	2022-05-24	12	-56/+52
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*	synth-vhdl_stmts: minor refactoring	Tristan Gingold	2022-05-24	1	-12/+23
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*	synth-vhdl_eval: handle element-element concatenation	Tristan Gingold	2022-05-24	1	-0/+18
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*	elab-vhdl_values-debug: slightly improve output	Tristan Gingold	2022-05-24	1	-2/+6
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*	testsuite/synth: add a comments	Tristan Gingold	2022-05-23	1	-0/+2
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*	synth-vhdl_stmts: rework synth_subprogram_association	Tristan Gingold	2022-05-23	1	-35/+35
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*	synth-vhdl_oper: add an hook for rising_edge	Tristan Gingold	2022-05-23	3	-4/+13
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*	elab-vhdl_objtypes: replace Is_Synth by Wkind	Tristan Gingold	2022-05-22	3	-23/+40
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*	synth: use same elements for unbounded arrays and vectors	Tristan Gingold	2022-05-22	9	-70/+36
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*	synth: also use one-dimensional unbounded arrays for objtypes	Tristan Gingold	2022-05-22	6	-58/+66
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*	synth: merge value for type_vector and type_array	Tristan Gingold	2022-05-22	15	-137/+113
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*	elab-vhdl_values-debug: improve debug_typ output	Tristan Gingold	2022-05-22	1	-14/+37
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*	synth: use unidimentional arrays in type_acc. Factorize code.	Tristan Gingold	2022-05-22	17	-552/+340
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*	synth-vhdl_stmts: write generic procedure Assign_Aggregate.	Tristan Gingold	2022-05-21	2	-14/+29
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*	synth-vhdl_expr: avoid a memocy copy	Tristan Gingold	2022-05-21	1	-3/+7
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*	vhdl-canon: remove unused canon_flag_inertial_associations	Tristan Gingold	2022-05-20	3	-9/+0
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*	synth/elab-vhdl_values: use a proper type for signal_index	Tristan Gingold	2022-05-19	5	-7/+11
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*	testsuite/synth: add a test for #2063	Tristan Gingold	2022-05-18	2	-0/+39
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*	synth-vhdl_stmts: avoid a crash after an error. Fix #2063	Tristan Gingold	2022-05-18	1	-1/+4
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*	synth-vhdl_stmts: add comments about report statements	Tristan Gingold	2022-05-18	1	-5/+51
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*	elab-vhdl_context: remove cur_stmt from context	Tristan Gingold	2022-05-17	2	-21/+0
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*	Merge pull request #2061 from cderrien/add_wall	tgingold	2022-05-17	1	-0/+9
\|\ \| \| \| \|	Add the -Wall flag.
\| *	Broken indentation.	cderrien	2022-05-17	1	-5/+5
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\| *	Add the -Wall flag.	cderrien	2022-05-16	1	-0/+9
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* \|	pyGHDL: requires TerminalUI <= 1.5.7	Tristan Gingold	2022-05-17	1	-1/+1
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* \|	vhdl-nodes: remove unused fields for procedure declarations	Tristan Gingold	2022-05-17	2	-219/+212
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* \|	vhdl: add suspend state pseudo decl and stmt. WIP.	Tristan Gingold	2022-05-17	8	-392/+444
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* \|	synth-vhdl_stmts: add a comment	Tristan Gingold	2022-05-17	1	-0/+2
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* \|	testsuite/synth: add a test for #2062	Tristan Gingold	2022-05-17	4	-0/+51
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* \|	synth-vhdl_oper: handle to_stdulogicvector for slv. Fix #2062	Tristan Gingold	2022-05-17	1	-0/+1
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* \|	vhdl-canon: refactoring.	Tristan Gingold	2022-05-16	2	-31/+87
\|/ \| \| \|	Export procedures to extract sensitivity from concurrent statements
*	Merge pull request #2058 from Xiretza/no-default-werror	tgingold	2022-05-16	5	-3/+7
\|\ \| \| \| \|	fix(configure): disable -Werror by default
\| *	fix(configure): disable -Werror by default	Xiretza	2022-05-16	5	-3/+7
\|/ \| \| \| \| \| \| \| \| \| \| \|	Because the build system does not have direct control over the compiler, it cannot ensure that no warnings are issued in downstream compilations. Such warnings can occur due to newer compiler versions with more sophisticated diagnostics, older compiler versions with diagnostics bugs, or simply different, untested compilers. With -Werror enabled by default, these harmless warnings result in complete compilation failures. The option remains enabled in CI to ensure upstream code quality.
*	vhdl-sem_specs: use by_name assoc for port default association	Tristan Gingold	2022-05-16	1	-1/+5
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*	ghdlcomp(common_compile_elab): add allow_undef_generic parameter	Tristan Gingold	2022-05-16	4	-4/+8
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*	elab-vhdl_debug(disp_instance_path): can also display components	Tristan Gingold	2022-05-16	2	-7/+23
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*	elab-vhdl_debug: factorize code, make Put_Dir public	Tristan Gingold	2022-05-16	2	-12/+6
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*	pyGHDL: limit pyTooling version to 1.10.0	Tristan Gingold	2022-05-15	3	-4/+4
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*	elab-vhdl_values: rename signal_index to signal_index_type	Tristan Gingold	2022-05-15	3	-5/+5
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*	pyGHDL: tentatively work-around incompatibility with pyTooling	Tristan Gingold	2022-05-15	1	-2/+2
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*	grt-readline_none.adb: do not use getline(3)	Tristan Gingold	2022-05-15	1	-19/+24
\| \| \| \|	Not available on windows.
*	elab-vhdl_values-debug: add disp_type_short	Tristan Gingold	2022-05-15	2	-8/+58
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*	elab-vhdl_debug: improve info signals	Tristan Gingold	2022-05-15	1	-20/+19
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*	elab-debugger: add append_info_menu, to_num	Tristan Gingold	2022-05-15	2	-5/+50
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*	trans_analyzes: add support for all processes	Tristan Gingold	2022-05-15	1	-85/+116
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*	elab-vhdl_debug(disp_instance_path): show top-level unit	Tristan Gingold	2022-05-15	1	-13/+5
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*	elab-debugger: add append_menu_command	Tristan Gingold	2022-05-15	2	-7/+29
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