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* elab-vhdl_objtypes: add unshare with areapoolTristan Gingold2022-05-292-0/+13
* synth: handle suspend state declaration and statementTristan Gingold2022-05-272-0/+16
* ghdlsimul: initial stop is after elaborationTristan Gingold2022-05-271-8/+1
* elab-debugger: add Debug_TimeTristan Gingold2022-05-272-1/+16
* elab-vhdl_debug: handle records in disp_memtyp.Tristan Gingold2022-05-272-4/+32
* elab-vhdl_objtypes: add Create_Memory_U32 (for states)Tristan Gingold2022-05-272-3/+19
* utils_io: add put_addr (to display addresses)Tristan Gingold2022-05-272-0/+24
* vhdl-canon: add Canon_Add_Suspend_StateTristan Gingold2022-05-2613-199/+574
* synth: move procedure call copyback values in contextTristan Gingold2022-05-253-79/+82
* vhdl-annotations: annotate procedure call associationsTristan Gingold2022-05-251-14/+47
* vhdl: move Is_Copyback_Parameter to vhdl-utilsTristan Gingold2022-05-253-12/+16
* synth: add value_dyn_alias in elab-vhdl_valuesTristan Gingold2022-05-258-72/+203
* elab-vhdl_objtypes: use value_offsets for record elements offset.Tristan Gingold2022-05-2412-56/+52
* synth-vhdl_stmts: minor refactoringTristan Gingold2022-05-241-12/+23
* synth-vhdl_eval: handle element-element concatenationTristan Gingold2022-05-241-0/+18
* elab-vhdl_values-debug: slightly improve outputTristan Gingold2022-05-241-2/+6
* testsuite/synth: add a commentsTristan Gingold2022-05-231-0/+2
* synth-vhdl_stmts: rework synth_subprogram_associationTristan Gingold2022-05-231-35/+35
* synth-vhdl_oper: add an hook for rising_edgeTristan Gingold2022-05-233-4/+13
* elab-vhdl_objtypes: replace Is_Synth by WkindTristan Gingold2022-05-223-23/+40
* synth: use same elements for unbounded arrays and vectorsTristan Gingold2022-05-229-70/+36
* synth: also use one-dimensional unbounded arrays for objtypesTristan Gingold2022-05-226-58/+66
* synth: merge value for type_vector and type_arrayTristan Gingold2022-05-2215-137/+113
* elab-vhdl_values-debug: improve debug_typ outputTristan Gingold2022-05-221-14/+37
* synth: use unidimentional arrays in type_acc. Factorize code.Tristan Gingold2022-05-2217-552/+340
* synth-vhdl_stmts: write generic procedure Assign_Aggregate.Tristan Gingold2022-05-212-14/+29
* synth-vhdl_expr: avoid a memocy copyTristan Gingold2022-05-211-3/+7
* vhdl-canon: remove unused canon_flag_inertial_associationsTristan Gingold2022-05-203-9/+0
* synth/elab-vhdl_values: use a proper type for signal_indexTristan Gingold2022-05-195-7/+11
* testsuite/synth: add a test for #2063Tristan Gingold2022-05-182-0/+39
* synth-vhdl_stmts: avoid a crash after an error. Fix #2063Tristan Gingold2022-05-181-1/+4
* synth-vhdl_stmts: add comments about report statementsTristan Gingold2022-05-181-5/+51
* elab-vhdl_context: remove cur_stmt from contextTristan Gingold2022-05-172-21/+0
* Merge pull request #2061 from cderrien/add_walltgingold2022-05-171-0/+9
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| * Broken indentation.cderrien2022-05-171-5/+5
| * Add the -Wall flag.cderrien2022-05-161-0/+9
* | pyGHDL: requires TerminalUI <= 1.5.7Tristan Gingold2022-05-171-1/+1
* | vhdl-nodes: remove unused fields for procedure declarationsTristan Gingold2022-05-172-219/+212
* | vhdl: add suspend state pseudo decl and stmt. WIP.Tristan Gingold2022-05-178-392/+444
* | synth-vhdl_stmts: add a commentTristan Gingold2022-05-171-0/+2
* | testsuite/synth: add a test for #2062Tristan Gingold2022-05-174-0/+51
* | synth-vhdl_oper: handle to_stdulogicvector for slv. Fix #2062Tristan Gingold2022-05-171-0/+1
* | vhdl-canon: refactoring.Tristan Gingold2022-05-162-31/+87
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* Merge pull request #2058 from Xiretza/no-default-werrortgingold2022-05-165-3/+7
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| * fix(configure): disable -Werror by defaultXiretza2022-05-165-3/+7
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* vhdl-sem_specs: use by_name assoc for port default associationTristan Gingold2022-05-161-1/+5
* ghdlcomp(common_compile_elab): add allow_undef_generic parameterTristan Gingold2022-05-164-4/+8
* elab-vhdl_debug(disp_instance_path): can also display componentsTristan Gingold2022-05-162-7/+23
* elab-vhdl_debug: factorize code, make Put_Dir publicTristan Gingold2022-05-162-12/+6
* pyGHDL: limit pyTooling version to 1.10.0Tristan Gingold2022-05-153-4/+4
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