diff options
Diffstat (limited to 'testsuite')
-rw-r--r-- | testsuite/synth/arr01/arr01.vhdl | 14 | ||||
-rw-r--r-- | testsuite/synth/arr01/arr02.vhdl | 14 | ||||
-rw-r--r-- | testsuite/synth/arr01/arr04.vhdl | 43 | ||||
-rw-r--r-- | testsuite/synth/arr01/tb_arr01.vhdl | 23 | ||||
-rw-r--r-- | testsuite/synth/arr01/tb_arr02.vhdl | 23 | ||||
-rw-r--r-- | testsuite/synth/arr01/tb_arr04.vhdl | 43 | ||||
-rwxr-xr-x | testsuite/synth/arr01/testsuite.sh | 16 |
7 files changed, 176 insertions, 0 deletions
diff --git a/testsuite/synth/arr01/arr01.vhdl b/testsuite/synth/arr01/arr01.vhdl new file mode 100644 index 000000000..be7d26e80 --- /dev/null +++ b/testsuite/synth/arr01/arr01.vhdl @@ -0,0 +1,14 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity arr01 is + port (v : std_logic_vector(7 downto 0); + h : out std_logic_vector(3 downto 0); + l : out std_logic_vector(3 downto 0)); +end arr01; + +architecture behav of arr01 is +begin + l <= v (3 downto 0); + h <= v (7 downto 4); +end behav; diff --git a/testsuite/synth/arr01/arr02.vhdl b/testsuite/synth/arr01/arr02.vhdl new file mode 100644 index 000000000..13447c779 --- /dev/null +++ b/testsuite/synth/arr01/arr02.vhdl @@ -0,0 +1,14 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity arr02 is + port (v : std_logic_vector(0 to 7); + h : out std_logic_vector(0 to 3); + l : out std_logic_vector(3 downto 0)); +end arr02; + +architecture behav of arr02 is +begin + l <= v (4 to 7); + h <= v (0 to 3); +end behav; diff --git a/testsuite/synth/arr01/arr04.vhdl b/testsuite/synth/arr01/arr04.vhdl new file mode 100644 index 000000000..813f366c9 --- /dev/null +++ b/testsuite/synth/arr01/arr04.vhdl @@ -0,0 +1,43 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity arr04 is + port (clk : in std_logic; + rst : std_logic; + sel_i : std_logic; + sel_o : std_logic; + v : std_logic; + res : out std_logic); +end arr04; + +architecture behav of arr04 is + signal reg : std_logic_vector (0 to 1); +begin + -- Reader + process(clk) + begin + if rising_edge (clk) then + if sel_o = '0' then + res <= reg (0); + else + res <= reg (1); + end if; + end if; + end process; + + -- Writer + process(clk) + begin + if rising_edge(clk) then + if rst = '1' then + reg <= "00"; + else + if sel_i = '0' then + reg (0) <= v; + else + reg (1) <= v; + end if; + end if; + end if; + end process; +end behav; diff --git a/testsuite/synth/arr01/tb_arr01.vhdl b/testsuite/synth/arr01/tb_arr01.vhdl new file mode 100644 index 000000000..bf3d7c6fa --- /dev/null +++ b/testsuite/synth/arr01/tb_arr01.vhdl @@ -0,0 +1,23 @@ +entity tb_arr01 is +end tb_arr01; + +library ieee; +use ieee.std_logic_1164.all; + +architecture behav of tb_arr01 is + signal v : std_logic_vector(7 downto 0); + signal h : std_logic_vector(3 downto 0); + signal l : std_logic_vector(3 downto 0); +begin + dut: entity work.arr01 + port map (v => v, h => h, l => l); + + process + begin + v <= x"e5"; + wait for 1 ns; + assert h = x"e" severity failure; + assert l = x"5" severity failure; + wait; + end process; +end behav; diff --git a/testsuite/synth/arr01/tb_arr02.vhdl b/testsuite/synth/arr01/tb_arr02.vhdl new file mode 100644 index 000000000..5dc615f40 --- /dev/null +++ b/testsuite/synth/arr01/tb_arr02.vhdl @@ -0,0 +1,23 @@ +entity tb_arr02 is +end tb_arr02; + +library ieee; +use ieee.std_logic_1164.all; + +architecture behav of tb_arr02 is + signal v : std_logic_vector(7 downto 0); + signal h : std_logic_vector(3 downto 0); + signal l : std_logic_vector(3 downto 0); +begin + dut: entity work.arr02 + port map (v => v, h => h, l => l); + + process + begin + v <= x"a7"; + wait for 1 ns; + assert h = x"a" severity failure; + assert l = x"7" severity failure; + wait; + end process; +end behav; diff --git a/testsuite/synth/arr01/tb_arr04.vhdl b/testsuite/synth/arr01/tb_arr04.vhdl new file mode 100644 index 000000000..51801b258 --- /dev/null +++ b/testsuite/synth/arr01/tb_arr04.vhdl @@ -0,0 +1,43 @@ +entity tb_arr04 is +end tb_arr04; + +library ieee; +use ieee.std_logic_1164.all; + +architecture behav of tb_arr04 is + signal clk : std_logic; + signal rst : std_logic; + signal sel_i : std_logic; + signal sel_o : std_logic; + signal v : std_logic; + signal r : std_logic; +begin + dut: entity work.arr04 + port map (clk => clk, rst => rst, sel_i => sel_i, sel_o => sel_o, + v => v, res => r); + + process + constant siv : std_logic_vector := b"0010"; + constant sov : std_logic_vector := b"0101"; + constant v_v : std_logic_vector := b"0011"; + constant r_v : std_logic_vector := b"0001"; + begin + clk <= '0'; + rst <= '1'; + wait for 1 ns; + clk <= '1'; + wait for 1 ns; + rst <= '0'; + for i in siv'range loop + sel_i <= siv (i); + sel_o <= sov (i); + v <= v_v (i); + clk <= '0'; + wait for 1 ns; + clk <= '1'; + wait for 1 ns; + assert r = r_v(i) severity failure; + end loop; + wait; + end process; +end behav; diff --git a/testsuite/synth/arr01/testsuite.sh b/testsuite/synth/arr01/testsuite.sh new file mode 100755 index 000000000..53b3a9116 --- /dev/null +++ b/testsuite/synth/arr01/testsuite.sh @@ -0,0 +1,16 @@ +#! /bin/sh + +. ../../testenv.sh + +for t in arr01 arr02 arr04; do + analyze $t.vhdl tb_$t.vhdl + elab_simulate tb_$t + clean + + synth $t.vhdl -e $t > syn_$t.vhdl + analyze syn_$t.vhdl tb_$t.vhdl + elab_simulate tb_$t + clean +done + +echo "Test successful" |