2 files changed, 34 insertions, 0 deletions
diff --git a/testsuite/gna/issue708/ent.vhdl b/testsuite/gna/issue708/ent.vhdl
new file mode 100644
index 000000000..17fe9cbef
--- /dev/null
+++ b/testsuite/gna/issue708/ent.vhdl
@@ -0,0 +1,24 @@
+library IEEE;
+use     IEEE.std_logic_1164.all;
+
+entity ent is
+end entity;
+
+architecture a of ent is
+    constant CHECK : natural := 4;
+    signal last : std_logic;
+    signal clk: std_logic;
+begin
+    process(clk)
+        variable i : natural range 0 to 127 := 0;
+    begin
+        if rising_edge(clk) then
+            if (((i+1) mod CHECK = 0) xor (last = '1')) then
+                report "Above line crashes";
+            end if;
+
+            i := i + 1;
+        end if;
+    end process;
+
+end architecture;
diff --git a/testsuite/gna/issue708/testsuite.sh b/testsuite/gna/issue708/testsuite.sh
new file mode 100755
index 000000000..9bc0d1b47
--- /dev/null
+++ b/testsuite/gna/issue708/testsuite.sh
@@ -0,0 +1,10 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+analyze ent.vhdl
+elab_simulate ent
+
+clean
+
+echo "Test successful"