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author | Tristan Gingold <tgingold@free.fr> | 2018-11-27 18:27:09 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2018-11-27 18:27:09 +0100 |
commit | c5f48631616aaa6b4c8a03031f0458fdcba90b68 (patch) | |
tree | 1c9dc5900da78d80c3c87da98d86a9b67936f82e /testsuite | |
parent | 8d37b8b9a068d60f61b1c3296c945afe5f252309 (diff) | |
download | ghdl-c5f48631616aaa6b4c8a03031f0458fdcba90b68.tar.gz ghdl-c5f48631616aaa6b4c8a03031f0458fdcba90b68.tar.bz2 ghdl-c5f48631616aaa6b4c8a03031f0458fdcba90b68.zip |
Add reproducer for #708
Diffstat (limited to 'testsuite')
-rw-r--r-- | testsuite/gna/issue708/ent.vhdl | 24 | ||||
-rwxr-xr-x | testsuite/gna/issue708/testsuite.sh | 10 |
2 files changed, 34 insertions, 0 deletions
diff --git a/testsuite/gna/issue708/ent.vhdl b/testsuite/gna/issue708/ent.vhdl new file mode 100644 index 000000000..17fe9cbef --- /dev/null +++ b/testsuite/gna/issue708/ent.vhdl @@ -0,0 +1,24 @@ +library IEEE; +use IEEE.std_logic_1164.all; + +entity ent is +end entity; + +architecture a of ent is + constant CHECK : natural := 4; + signal last : std_logic; + signal clk: std_logic; +begin + process(clk) + variable i : natural range 0 to 127 := 0; + begin + if rising_edge(clk) then + if (((i+1) mod CHECK = 0) xor (last = '1')) then + report "Above line crashes"; + end if; + + i := i + 1; + end if; + end process; + +end architecture; diff --git a/testsuite/gna/issue708/testsuite.sh b/testsuite/gna/issue708/testsuite.sh new file mode 100755 index 000000000..9bc0d1b47 --- /dev/null +++ b/testsuite/gna/issue708/testsuite.sh @@ -0,0 +1,10 @@ +#! /bin/sh + +. ../../testenv.sh + +analyze ent.vhdl +elab_simulate ent + +clean + +echo "Test successful" |