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Diffstat (limited to 'testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling')
23 files changed, 1575 insertions, 0 deletions
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/index-ams.txt b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/index-ams.txt new file mode 100644 index 000000000..16e7ad519 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/index-ams.txt @@ -0,0 +1,36 @@ +--------------------------------------------------------------------------------------------------------------------------------------------- +-- Chapter 13 - Frequency and Transfer Function Modeling +--------------------------------------------------------------------------------------------------------------------------------------------- +-- Filename Primary Unit Secondary Unit Figure/Section +----------- ------------ -------------- -------------- +v_source.vhd entity v_source behavior Figure 13-3 +v_source-1.vhd entity v_source behavior Figure 13-4 +nmos_transistor.vhd entity NMOS_transistor noisy Figure 13-5 +nmos_transistor_wa.vhd entity nmos_transistor_wa noisy -- +lowpass-1.vhd entity resistor ideal -- +-- entity capacitor ideal -- +-- entity lowpass RC Figure 13-7 +lowpass-2.vhd entity lowpass dot Figure 13-9 +lowpass-3.vhd entity lowpass ltf Figure 13-11 +opamp.vhd entity opamp slew_limited Figure 13-13 +opamp_2pole.vhd entity opamp_2pole dot, ltf Figure 13-15 +opamp_2pole_res.vhd entity opamp_2pole_res ltf Figure 13-16 +lowpass-4.vhd entity lowpass z_minus_1 Figure 13-17 +lowpass-5.vhd entity lowpass ztf Figure 13-19 +lowpass.vhd entity lowpass RC, dot, ltf, z_minus_1, ztf Figure 13-22 +inline_01a.vhd entity inline_01a test Section 13.1 +inline_02a.vhd entity inline_02a test Section 13.2 +inline_03a.vhd entity inline_03a test Section 13.3 +--------------------------------------------------------------------------------------------------------------------------------------------- +-- TestBenches +--------------------------------------------------------------------------------------------------------------------------------------------- +-- Filename Primary Unit Secondary Unit Tested Model +------------ ------------ -------------- ------------ +tb_v_source.vhd entity tb_v_source TB_v_source v_source.vhd +tb_mosfet_noisy.vhd entity tb_mosfet_noisy TB_mosfet_noisy nmos_transistor_wa.vhd +tb_opamp.vhd entity tb_opamp TB_opamp opamp.vhd +tb_opamp_2pole.vhd entity tb_opamp_2pole TB_opamp_2pole opamp_2pole.vhd +tb_lpf_dot_ltf_ztf-1.vhd entity tb_lpf_dot_ltf_ztf TB_lpf_dot_ltf_ztf lowpass-1.vhd, lowpass-2.vhd, +-- lowpass-3.vhd, lowpass-4.vhd, +-- lowpass-5.vhd +tb_lpf_dot_ltf_ztf.vhd entity tb_lpf_dot_ltf_ztf TB_lpf_dot_ltf_ztf lowpass.vhd diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/inline_01a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/inline_01a.vhd new file mode 100644 index 000000000..c6e2a9c25 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/inline_01a.vhd @@ -0,0 +1,63 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee_proposed; use ieee_proposed.electrical_systems.all; +library ieee; use ieee.math_real.all; + +entity inline_01a is + +end entity inline_01a; + + +architecture test of inline_01a is + + function inverse_exp ( x : real ) return real is + begin + return 10.0 * exp(-2.0e-6 * x); + end function inverse_exp; + + -- code from book + + type domain_type is (quiescent_domain, time_domain, frequency_domain); + + -- + + quantity spec_source : real spectrum 2.5, math_pi / 2.0; + + -- + + function frequency return real; + + -- + + quantity source1 : real spectrum inverse_exp(frequency), math_pi / 4.0; + + -- + + quantity source2 : real spectrum 5.0, 1.0E-6 * frequency / math_pi; + + -- end code from book + + function frequency return real is + begin + return std.standard.frequency; + end function frequency; + +begin +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/inline_02a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/inline_02a.vhd new file mode 100644 index 000000000..6864aaa27 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/inline_02a.vhd @@ -0,0 +1,71 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee; use ieee.math_real.all; +library ieee_proposed; use ieee_proposed.electrical_systems.all; +use ieee_proposed.energy_systems.all; + + +entity inline_02a is + +end entity inline_02a; + + +architecture test of inline_02a is + + constant k_Boltzmann : real := K; + constant temp : real := 300.0; + constant res : real := 10_000.0; + terminal r_p1, r_p2 : electrical; + quantity resistor_voltage across resistor_current through r_p1 to r_p2; + + constant k_noise : real := 1.0; + + function G ( f : real ) return real is + begin + return 1.0; + end function G; + + constant k_flicker : real := 1.0; + constant ids : real := 0.01; + constant af : real := 1.0; + + -- code from book + + quantity thermal_noise_source : real noise 4.0 * k_Boltzmann * temp * res; + + -- + + quantity shaped_noise_source : real noise k_noise * temp * G(frequency); + + -- + + quantity flicker_noise_source : real noise k_flicker * ids**af / frequency; + + -- end code from book + +begin + + -- code from book + + resistor_voltage == resistor_current * res + thermal_noise_source; + + -- end code from book + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/inline_03a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/inline_03a.vhd new file mode 100644 index 000000000..e9889f00c --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/inline_03a.vhd @@ -0,0 +1,39 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee_proposed; use ieee_proposed.electrical_systems.all; +library ieee; use ieee.math_real.all; + +entity inline_03a is + +end entity inline_03a; + + +architecture test of inline_03a is + + -- code from book + + constant fp : real := 10.0; -- filter pole in hertz + constant wp : real := math_2_pi * fp; -- filter pole in rad/s + constant tp : real := 1.0 / wp; -- filter time constant + + -- end code from book + +begin +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/lowpass-1.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/lowpass-1.vhd new file mode 100644 index 000000000..c47c772e9 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/lowpass-1.vhd @@ -0,0 +1,72 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- not in book + +library ieee_proposed; use ieee_proposed.electrical_systems.all; + +entity resistor is + generic ( res : resistance ); + port ( terminal p1, p2 : electrical ); +end entity resistor; + +architecture ideal of resistor is + quantity v across i through p1 to p2; +begin + v == i * res; +end architecture ideal; + + +library ieee_proposed; use ieee_proposed.electrical_systems.all; + +entity capacitor is + generic ( cap : resistance ); + port ( terminal p1, p2 : electrical ); +end entity capacitor; + +architecture ideal of capacitor is + quantity v across i through p1 to p2; +begin + i == cap * v'dot; +end architecture ideal; + +-- end not in book + + +library ieee_proposed; use ieee_proposed.electrical_systems.all; + +entity lowpass is + port ( terminal input : electrical; + terminal output : electrical ); +end entity lowpass; + +---------------------------------------------------------------- + +architecture RC of lowpass is +begin + + R : entity work.resistor(ideal) + generic map ( res => 15.9e3 ) + port map ( p1 => input, p2 => output ); + + C : entity work.capacitor(ideal) + generic map ( cap => 1.0e-6 ) + port map ( p1 => output, p2 => electrical_ref ); + +end architecture RC; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/lowpass-2.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/lowpass-2.vhd new file mode 100644 index 000000000..51624706c --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/lowpass-2.vhd @@ -0,0 +1,39 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee_proposed; use ieee_proposed.electrical_systems.all; + +entity lowpass is + port ( terminal input : electrical; + terminal output : electrical ); +end entity lowpass; + +---------------------------------------------------------------- + +architecture dot of lowpass is + + quantity vin across input to electrical_ref; + quantity vout across iout through output to electrical_ref; + constant tp : real := 15.9e-3; -- filter time constant + +begin + + vin == vout + tp * vout'dot; + +end architecture dot; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/lowpass-3.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/lowpass-3.vhd new file mode 100644 index 000000000..9a1cbfa02 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/lowpass-3.vhd @@ -0,0 +1,42 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee_proposed; use ieee_proposed.electrical_systems.all; +library ieee; use ieee.math_real.all; + +entity lowpass is + port ( terminal input : electrical; + terminal output : electrical ); +end entity lowpass; + +---------------------------------------------------------------- + +architecture ltf of lowpass is + + quantity vin across input to electrical_ref; + quantity vout across iout through output to electrical_ref; + constant wp : real := 10.0 * math_2_pi; -- pole in rad/s + constant num : real_vector := (0 => wp); -- numerator in s + constant den : real_vector := (wp, 1.0); -- denominator in s + +begin + + vout == vin'ltf(num, den); + +end architecture ltf; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/lowpass-4.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/lowpass-4.vhd new file mode 100644 index 000000000..666d100e8 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/lowpass-4.vhd @@ -0,0 +1,55 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee; use ieee.math_real.all; +library ieee_proposed; use ieee_proposed.electrical_systems.all; + +entity lowpass is + generic ( fp : real := 10.0; -- pole in Hz for 'zoh, 'delayed + Fsmp : real := 10.0e3 ); -- sample frequency for 'zoh, 'delayed + port ( terminal input : electrical; + terminal output: electrical ); +end entity lowpass; + +---------------------------------------------------------------- + +architecture z_minus_1 of lowpass is + + quantity vin across input to electrical_ref; + quantity vout across iout through output to electrical_ref; + quantity vin_sampled : real; -- discrete sample of input quantity + quantity vin_zm1, vout_zm1 : real; -- z**-1 + constant Tsmp : real := 1.0 / Fsmp; -- sample period + constant wp : real := fp * math_2_pi; -- pole in rad/s + constant n0 : real := Tsmp * wp; -- z0 numerator coefficient + constant n1 : real := Tsmp * wp; -- z-1 numerator coefficient + constant d0 : real := Tsmp * wp + 2.0; -- z0 denominator coefficient + constant d1 : real := Tsmp * wp - 2.0; -- z-1 denominator coefficient + +begin + + vin_sampled == vin'zoh(Tsmp); + + vin_zm1 == vin_sampled'delayed(Tsmp); + + vout_zm1 == vout'delayed(Tsmp); + + vout == vin_sampled * n0 / d0 + n1 * vin_zm1 / d0 - d1 * vout_zm1 / d0; + +end z_minus_1; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/lowpass-5.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/lowpass-5.vhd new file mode 100644 index 000000000..d1f655c62 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/lowpass-5.vhd @@ -0,0 +1,49 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee; use ieee.math_real.all; +library ieee_proposed; use ieee_proposed.electrical_systems.all; + +entity lowpass is + generic ( fp : real := 10.0; -- pole in Hz for 'ztf + Fsmp : real := 10.0e3); -- sample frequency for 'ztf + port ( terminal input: electrical; + terminal output: electrical ); +end entity lowpass; + +---------------------------------------------------------------- + +architecture ztf of lowpass is + + quantity vin across input to electrical_ref; + quantity vout across iout through output to electrical_ref; + constant Tsmp : real := 1.0 / Fsmp; -- sample period + constant wp : real := fp * math_2_pi; -- pole in rad/s + constant n0 : real := Tsmp * wp; -- z0 numerator coefficient (a) + constant n1 : real := Tsmp * wp; -- z-1 numerator coefficient (b) + constant d0 : real := Tsmp * wp + 2.0; -- z0 denominator coefficient (c) + constant d1 : real := Tsmp * wp - 2.0; -- z-1 denominator coefficient (d) + constant num : real_vector := (n0, n1); + constant den : real_vector := (d0, d1); + +begin + + vout == vin'ztf(num, den, Tsmp); + +end ztf; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/lowpass.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/lowpass.vhd new file mode 100644 index 000000000..e553f1752 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/lowpass.vhd @@ -0,0 +1,170 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- not in book + +library ieee_proposed; use ieee_proposed.electrical_systems.all; + +entity resistor is + generic ( res : resistance ); + port ( terminal p1, p2 : electrical ); +end entity resistor; + +architecture ideal of resistor is + quantity v across i through p1 to p2; +begin + v == i * res; +end architecture ideal; + + +library ieee_proposed; use ieee_proposed.electrical_systems.all; + +entity capacitor is + generic ( cap : resistance ); + port ( terminal p1, p2 : electrical ); +end entity capacitor; + +architecture ideal of capacitor is + quantity v across i through p1 to p2; +begin + i == cap * v'dot; +end architecture ideal; + +-- end not in book + + +library ieee; use ieee.math_real.all; +library ieee_proposed; use ieee_proposed.electrical_systems.all; + +entity lowpass is + generic ( gain : real := 1.0; -- gain for 'dot, 'ltf, and 'ztf + fp : real := 10.0; -- pole in Hz for 'dot, 'ltf, and 'ztf + Fsmp : real := 10.0e3 ); -- sample frequency for ztf + port ( terminal input: electrical; + terminal output: electrical ); +end entity lowpass; + +---------------------------------------------------------------- + +architecture RC of lowpass is + + constant cap : real := 1.0e-6; + constant res : real := 1.0 / (math_2_pi * cap * fp); + +begin + + assert false + report "gain is ignored in architecture RC" severity note; + assert false + report "Fsmp is not used in architecture RC" severity note; + + R : entity work.resistor(ideal) + generic map( res => res ) + port map( p1 => input, p2 => output ); + + C : entity work.capacitor(ideal) + generic map( cap => cap ) + port map( p1 => output, p2 => electrical_ref ); + +end architecture RC; + +---------------------------------------------------------------- + +architecture dot of lowpass is + + quantity vin across input to electrical_ref; + quantity vout across iout through output to electrical_ref; + constant wp : real := fp * math_2_pi; -- pole in rad/s + constant tp : real := 1.0 / wp; -- time constant + +begin + + assert false + report "Fsmp is not used in architecture dot" severity note; + + vin == (vout + tp * vout'dot) / gain; + +end architecture dot; + +---------------------------------------------------------------- + +architecture ltf of lowpass is + + quantity vin across input to electrical_ref; + quantity vout across iout through output to electrical_ref; + constant wp : real := fp * math_2_pi; -- pole in rad/s + constant num : real_vector := (0 => wp); + constant den : real_vector := (wp, 1.0); + +begin + + assert false + report "Fsmp is not used in architecture ltf" severity note; + + vout == gain*vin'ltf(num, den); + +end architecture ltf; + +---------------------------------------------------------------- + +architecture z_minus_1 of lowpass is + + quantity vin across input to electrical_ref; + quantity vout across iout through output to electrical_ref; + quantity vin_sampled : real; -- sampled input + quantity vin_zm1, vout_zm1 : real; -- z**-1 + constant Tsmp : real := 1.0 / Fsmp; -- sample period + constant wp : real := fp * math_2_pi; -- pole in rad/s + constant n0 : real := Tsmp * wp; -- z0 numerator coefficient + constant n1 : real := Tsmp * wp; -- z-1 numerator coefficient + constant d0 : real := Tsmp * wp + 2.0; -- z0 denominator coefficient + constant d1 : real := Tsmp * wp - 2.0; -- z-1 denominator coefficient + +begin + + vin_sampled == gain*vin'zoh(Tsmp); + + vin_zm1 == vin_sampled'delayed(Tsmp); + + vout_zm1 == vout'delayed(Tsmp); + + vout == vin_sampled * n0 / d0 + n1 * vin_zm1 / d0 - d1 * vout_zm1 / d0; + +end z_minus_1; + +---------------------------------------------------------------- + +architecture ztf of lowpass is + + quantity vin across input to electrical_ref; + quantity vout across iout through output to electrical_ref; + constant Tsmp : real := 1.0 / Fsmp; -- sample period + constant wp : real := fp * math_2_pi; -- pole in rad/s + constant n0 : real := Tsmp * wp; -- z0 numerator coefficient + constant n1 : real := Tsmp * wp; -- z-1 numerator coefficient + constant d0 : real := Tsmp * wp + 2.0; -- z0 denominator coefficient + constant d1 : real := Tsmp * wp - 2.0; -- z-1 denominator coefficient + constant num : real_vector := (n0, n1); + constant den : real_vector := (d0, d1); + +begin + + vout == gain*vin'ztf(num, den, Tsmp); + +end ztf; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/nmos_transistor.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/nmos_transistor.vhd new file mode 100644 index 000000000..763e46d73 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/nmos_transistor.vhd @@ -0,0 +1,82 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee; use ieee.math_real.all; +library ieee_proposed; use ieee_proposed.electrical_systems.all; + +entity NMOS_transistor is + generic ( Cgs : real := 1.0e-6; -- gate to source capacitance + Cgd : real := 1.0e-6; -- gate to drain capacitance + gm : real := 5.0e-4; -- transconductance + temp : real := 1.0; -- termperature + Ro : real := 500.0e3; -- ro resistance + af : real := 1.0; -- flicker noise exponent constant + k_flicker : real := 1.0 ); -- flicker noise constant + port ( terminal gate, drain, source : electrical ); +end entity NMOS_transistor; + +---------------------------------------------------------------- + +architecture noisy of NMOS_transistor is + + quantity vgs across igs through gate to source; + quantity vds across ids through drain to source; + quantity vsd across source to drain; + quantity vgd across igd through gate to drain; + constant threshold_voltage : voltage := 1.0; + constant k : real := 1.0e-5; + -- declare quantity in frequency domain for AC analysis + quantity MOS_noise_source : real noise + 4.0*K*temp/Ro + -- thermal noise + k_flicker*ids**af/frequency; -- flicker noise + +begin + + if domain = quiescent_domain or domain = time_domain use + + if vds >= 0.0 use -- transistor is forward biased + if vgs < threshold_voltage use -- cutoff region + ids == 0.0; + elsif vds > vgs - threshold_voltage use -- saturation region + ids == 0.5 * k * (vgs - threshold_voltage)**2; + else -- linear/triode region + ids == k * (vgs - threshold_voltage - 0.5*vds) * vds; + end use; + else -- transistor is reverse biased + if vgd < threshold_voltage use -- cutoff region + ids == 0.0; + elsif vsd > vgd - threshold_voltage use -- saturation region + ids == -0.5 * k * (vgd - threshold_voltage)**2; + else -- linear/triode region + ids == -k * (vgd - threshold_voltage - 0.5*vsd) * vsd; + end use; + end use; + + igs == 0.0; + igd == 0.0; + + else -- noise and frequency model + + igs == Cgs*vgs'dot; + igd == Cgd*vgd'dot; + ids == gm*vgs + vds/Ro + MOS_noise_source; + + end use; + +end architecture noisy; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/nmos_transistor_wa.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/nmos_transistor_wa.vhd new file mode 100644 index 000000000..f5223e620 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/nmos_transistor_wa.vhd @@ -0,0 +1,61 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee_proposed; use ieee_proposed.electrical_systems.all; + +entity NMOS_transistor_wa is + port ( terminal gate, drain, source : electrical ); +end entity NMOS_transistor_wa; + +---------------------------------------------------------------- + +architecture noisy of NMOS_transistor_wa is + + quantity vgs across igs through gate to source; + quantity vds across ids through drain to source; + quantity vsd across source to drain; + quantity vgd across igd through gate to drain; + constant threshold_voltage : voltage := 1.0; + constant k : real := 1.0e-5; + -- declare quantity in frequency domain for AC analysis + +begin + + if vds >= 0.0 use -- transistor is forward biased + if vgs < threshold_voltage use -- cutoff region + ids == 0.0; + elsif vds > vgs - threshold_voltage use -- saturation region + ids == 0.5 * k * (vgs - threshold_voltage)**2; + else -- linear/triode region + ids == k * (vgs - threshold_voltage - 0.5*vds) * vds; + end use; + else -- transistor is reverse biased + if vgd < threshold_voltage use -- cutoff region + ids == 0.0; + elsif vsd > vgd - threshold_voltage use -- saturation region + ids == -0.5 * k * (vgd - threshold_voltage)**2; + else -- linear/triode region + ids == -k * (vgd - threshold_voltage - 0.5*vsd) * vsd; + end use; + end use; + + igs == 0.0; + igd == 0.0; + +end architecture noisy; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/opamp.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/opamp.vhd new file mode 100644 index 000000000..4a7799c8d --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/opamp.vhd @@ -0,0 +1,41 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee_proposed; use ieee_proposed.electrical_systems.all; + +entity opamp is + port ( terminal plus_in, minus_in, output : electrical ); +end entity opamp; + +---------------------------------------------------------------- + +architecture slew_limited of opamp is + + constant gain : real := 50.0; + quantity v_in across plus_in to minus_in; + quantity v_out across i_out through output; + quantity v_amplified : voltage; + +begin + + v_amplified == gain * v_in; + + v_out == v_amplified'slew(1.0e6,-1.0e6); + +end architecture slew_limited; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/opamp_2pole.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/opamp_2pole.vhd new file mode 100644 index 000000000..8bef2bb8f --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/opamp_2pole.vhd @@ -0,0 +1,64 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee; use ieee.math_real.all; +library ieee_proposed; use ieee_proposed.electrical_systems.all; + +entity opamp_2pole is + port ( terminal in_pos, in_neg, output : electrical ); +end entity opamp_2pole; + +---------------------------------------------------------------- + +architecture dot of opamp_2pole is + + constant A : real := 1.0e6; -- open loop gain + constant fp1 : real := 5.0; -- first pole + constant fp2 : real := 9.0e5; -- second pole + constant tp1 : real := 1.0 / (fp1 * math_2_pi); -- first time constant + constant tp2 : real := 1.0 / (fp2 * math_2_pi); -- second time constant + quantity v_in across in_pos to in_neg; + quantity v_out across i_out through output; + +begin + + v_in == (tp1 * tp2) * v_out'dot'dot / A + + (tp1 + tp2) * v_out'dot / A + v_out / A; + +end architecture dot; + +---------------------------------------------------------------- + +architecture ltf of opamp_2pole is + + constant A : real := 1.0e6; -- open loop gain + constant fp1 : real := 5.0; -- first pole (Hz) + constant fp2 : real := 9.0e5; -- second pole (Hz) + constant wp1 : real := fp1 * math_2_pi; -- first pole (rad/s) + constant wp2 : real := fp2 * math_2_pi; -- second pole (rad/s) + constant num : real_vector := (0 => wp1 * wp2 * A); + constant den : real_vector := (wp1 * wp2, wp1 + wp2, 1.0); + quantity v_in across in_pos to in_neg; + quantity v_out across i_out through output; + +begin + + v_out == v_in'ltf(num, den); + +end architecture ltf; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/opamp_2pole_res.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/opamp_2pole_res.vhd new file mode 100644 index 000000000..60ac210bb --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/opamp_2pole_res.vhd @@ -0,0 +1,49 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee; use ieee.math_real.all; +library ieee_proposed; use ieee_proposed.electrical_systems.all; + +entity opamp_2pole_res is + generic ( A : real := 1.0e6; -- open loop gain + rin : real := 1.0e6; -- input resistance + rout : real := 100.0; -- output resistance + fp1 : real := 5.0; -- first pole + fp2 : real := 9.0e5 ); -- second pole + port ( terminal in_pos, in_neg, output : electrical ); +end entity opamp_2pole_res; + +---------------------------------------------------------------- + +architecture ltf of opamp_2pole_res is + + constant wp1 : real := fp1 * math_2_pi; + constant wp2 : real := fp2 * math_2_pi; + constant num : real_vector := (0 => wp1 * wp2 * A); + constant den : real_vector := (wp1 * wp2, wp1 + wp2, 1.0); + quantity v_in across i_in through in_pos to in_neg; + quantity v_out across i_out through output; + +begin + + i_in == v_in / rin; -- input current + + v_out == v_in'ltf(num, den) + i_out * rout; + +end architecture ltf; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/tb_lpf_dot_ltf_ztf-1.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/tb_lpf_dot_ltf_ztf-1.vhd new file mode 100644 index 000000000..a26499e6d --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/tb_lpf_dot_ltf_ztf-1.vhd @@ -0,0 +1,76 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library IEEE; +use IEEE.std_logic_1164.all; +library IEEE_proposed; +use IEEE_proposed.electrical_systems.all; + +entity tb_lpf_dot_ltf_ztf is +end tb_lpf_dot_ltf_ztf; + +architecture TB_lpf_dot_ltf_ztf of tb_lpf_dot_ltf_ztf is + -- Component declarations + -- Signal declarations + terminal in_src : electrical; + terminal out_dot, out_ltf, out_ztf1, out_ztf4, out_RC : electrical; +begin + -- Signal assignments + -- Component instances + vio : entity work.v_sine(ideal) + generic map( + freq => 100.0, + amplitude => 5.0 + ) + port map( + pos => in_src, + neg => ELECTRICAL_REF + ); + + RC1 : entity work.lowpass(RC) + + port map( + input => in_src, + output => out_RC + ); + dot1 : entity work.lowpass(dot) + + port map( + input => in_src, + output => out_dot + ); + ltf1 : entity work.lowpass(ltf) + + port map( + input => in_src, + output => out_ltf + ); + ztf1 : entity work.lowpass(ztf) + + port map( + input => in_src, + output => out_ztf1 + ); + ztf4 : entity work.lowpass(z_minus_1) + + port map( + input => in_src, + output => out_ztf4 + ); +end TB_lpf_dot_ltf_ztf; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/tb_lpf_dot_ltf_ztf.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/tb_lpf_dot_ltf_ztf.vhd new file mode 100644 index 000000000..be639a4e6 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/tb_lpf_dot_ltf_ztf.vhd @@ -0,0 +1,115 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library IEEE; +use IEEE.std_logic_1164.all; +library IEEE_proposed; +use IEEE_proposed.electrical_systems.all; + +entity tb_lpf_dot_ltf_ztf is +end tb_lpf_dot_ltf_ztf; + +architecture TB_lpf_dot_ltf_ztf of tb_lpf_dot_ltf_ztf is + -- Component declarations + -- Signal declarations + terminal in_src : electrical; + terminal out_dot, out_ltf, out_ztf1, out_ztf2, out_ztf3, out_ztf4, out_RC : electrical; +begin + -- Signal assignments + -- Component instances + vio : entity work.v_sine(ideal) + generic map( + freq => 100.0, + amplitude => 5.0 + ) + port map( + pos => in_src, + neg => ELECTRICAL_REF + ); + RC1 : entity work.lowpass(RC) + generic map( + gain => 1.0, + fp => 1.0e1, + Fsmp => 10.0e3 + ) + port map( + input => in_src, + output => out_RC + ); + dot1 : entity work.lowpass(dot) + generic map( + gain => 1.0, + fp => 1.0e1, + Fsmp => 10.0e3 + ) + port map( + input => in_src, + output => out_dot + ); + ltf1 : entity work.lowpass(ltf) + generic map( + gain => 1.0, + fp => 1.0e1, + Fsmp => 10.0e3 + ) + port map( + input => in_src, + output => out_ltf + ); + ztf1 : entity work.lowpass(ztf) + generic map( + gain => 1.0, + fp => 1.0e1, + Fsmp => 10.0e3 + ) + port map( + input => in_src, + output => out_ztf1 + ); + ztf2 : entity work.lowpass(ztf) + generic map( + gain => 1.0, + fp => 1.0e1, + Fsmp => 1000.0 + ) + port map( + input => in_src, + output => out_ztf2 + ); + ztf3 : entity work.lowpass(ztf) + generic map( + gain => 1.0, + fp => 1.0e1, + Fsmp => 100.0 + ) + port map( + input => in_src, + output => out_ztf3 + ); + ztf4 : entity work.lowpass(z_minus_1) + generic map( + gain => 1.0, + fp => 1.0e1, + Fsmp => 10.0e3 + ) + port map( + input => in_src, + output => out_ztf4 + ); +end TB_lpf_dot_ltf_ztf; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/tb_mosfet_noisy.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/tb_mosfet_noisy.vhd new file mode 100644 index 000000000..ebc499062 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/tb_mosfet_noisy.vhd @@ -0,0 +1,72 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_arith.all; + +library IEEE_proposed; +use IEEE_proposed.electrical_systems.all; + +entity tb_mosfet_noisy is +end tb_mosfet_noisy ; + +architecture TB_mosfet_noisy of tb_mosfet_noisy is + -- Component declarations + -- Signal declarations + terminal d : electrical; + terminal g : electrical; +begin + -- Signal assignments + -- Component instances + mosfet1 : entity work.nmos_transistor_wa(noisy) + port map( + gate => g, + drain => d, + source => ELECTRICAL_REF + ); + v1 : entity work.v_constant(ideal) + generic map( + level => 4.0 + ) + port map( + pos => g, + neg => ELECTRICAL_REF + ); + mosfet2 : entity work.nmos_transistor_wa(noisy) + port map( + gate => g, + drain => ELECTRICAL_REF, + source => d + ); + v4 : entity work.v_pulse(ideal) + generic map( + initial => 0.0, + pulse => 5.0, + ti2p => 1 ms, + tp2i => 1 ms, + delay => 1 us, + width => 1 us, + period => 2.002 ms + ) + port map( + pos => d, + neg => ELECTRICAL_REF + ); +end TB_mosfet_noisy ; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/tb_opamp.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/tb_opamp.vhd new file mode 100644 index 000000000..9be54df36 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/tb_opamp.vhd @@ -0,0 +1,74 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library IEEE; use IEEE.std_logic_1164.all; +library IEEE_proposed; use IEEE_proposed.electrical_systems.all; + +entity tb_opamp is +end tb_opamp; + +architecture TB_opamp of tb_opamp is + -- Component declarations + -- Signal declarations + terminal in_src, op_neg2, out_opamp2 : electrical; + terminal out_opamp1, op_neg1, op_neg3, out_opamp3, out_opamp3_res, op_neg3_res : electrical; +begin + -- Signal assignments + -- Component instances + vio : entity work.v_sine(ideal) + generic map( + freq => 100.0, + amplitude => 5.0e-3 + ) + port map( + pos => in_src, + neg => ELECTRICAL_REF + ); + + OP1 : entity work.opamp(slew_limited) + port map( + plus_in => electrical_ref, + minus_in => op_neg1, + output => out_opamp1 + ); + R1in : entity work.resistor(ideal) + generic map( + res => 10.0e3 + ) + port map( + p1 => in_src, + p2 => op_neg1 + ); + R1F : entity work.resistor(ideal) + generic map( + res => 10.0e9 + ) + port map( + p1 => op_neg1, + p2 => out_opamp1 + ); + Rload1 : entity work.resistor(ideal) + generic map( + res => 1.0e3 + ) + port map( + p1 => out_opamp1, + p2 => electrical_ref + ); +end TB_opamp; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/tb_opamp_2pole.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/tb_opamp_2pole.vhd new file mode 100644 index 000000000..ddb9c5e1b --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/tb_opamp_2pole.vhd @@ -0,0 +1,134 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library IEEE; use IEEE.std_logic_1164.all; +library IEEE_proposed; use IEEE_proposed.electrical_systems.all; + +entity tb_opamp_2pole is +end tb_opamp_2pole; + +architecture TB_opamp_2pole of tb_opamp_2pole is + -- Component declarations + -- Signal declarations + terminal in_src, op_neg2, out_opamp2 : electrical; + terminal out_opamp1, op_neg1, out_opamp3_res, op_neg3_res : electrical; +begin + -- Signal assignments + -- Component instances + vio : entity work.v_sine(ideal) + generic map( + freq => 100.0, + amplitude => 5.0 + ) + port map( + pos => in_src, + neg => ELECTRICAL_REF + ); + + OP1 : entity work.opamp_2pole(dot) + port map( + in_pos => electrical_ref, + in_neg => op_neg1, + output => out_opamp1 + ); + R1in : entity work.resistor(ideal) + generic map( + res => 10.0e3 + ) + port map( + p1 => in_src, + p2 => op_neg1 + ); + R1F : entity work.resistor(ideal) + generic map( + res => 10.0e3 + ) + port map( + p1 => op_neg1, + p2 => out_opamp1 + ); + Rload1 : entity work.resistor(ideal) + generic map( + res => 1.0e3 + ) + port map( + p1 => out_opamp1, + p2 => electrical_ref + ); + OP2 : entity work.opamp_2pole(ltf) + port map( + in_pos => electrical_ref, + in_neg => op_neg2, + output => out_opamp2 + ); + R2in : entity work.resistor(ideal) + generic map( + res => 10.0e3 + ) + port map( + p1 => in_src, + p2 => op_neg2 + ); + R2F : entity work.resistor(ideal) + generic map( + res => 10.0e3 + ) + port map( + p1 => op_neg2, + p2 => out_opamp2 + ); + Rload2 : entity work.resistor(ideal) + generic map( + res => 1.0e3 + ) + port map( + p1 => out_opamp2, + p2 => electrical_ref + ); + OP3R : entity work.opamp_2pole_res(ltf) + port map( + in_pos => electrical_ref, + in_neg => op_neg3_res, + output => out_opamp3_res + ); + Rin3R : entity work.resistor(ideal) + generic map( + res => 10.0e3 + ) + port map( + p1 => in_src, + p2 => op_neg3_res + ); + R3F : entity work.resistor(ideal) + generic map( + res => 10.0e3 + ) + port map( + p1 => op_neg3_res, + p2 => out_opamp3_res + ); + Rload3R : entity work.resistor(ideal) + generic map( + res => 1.0e3 + ) + port map( + p1 => out_opamp3_res, + p2 => electrical_ref + ); +end TB_opamp_2pole; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/tb_v_source.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/tb_v_source.vhd new file mode 100644 index 000000000..17a776552 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/tb_v_source.vhd @@ -0,0 +1,67 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library IEEE_proposed; +use IEEE_proposed.electrical_systems.all; + +entity tb_v_source is + +end tb_v_source ; + +architecture TB_v_source of tb_v_source is + terminal sin_out1, sin_out2 : electrical; + -- Component declarations + -- Signal declarations +begin + -- Signal assignments + -- Component instances + v1 : entity work.v_source(behavior) + port map( + pos => sin_out1, + neg => ELECTRICAL_REF + ); + + R1 : entity work.resistor(ideal) + generic map( + res => 10.0e3 + ) + port map( + p1 => sin_out1, + p2 => electrical_ref + ); + v2 : entity work.v_constant(ideal) + generic map( + level => 1.0 + ) + port map( + pos => sin_out2, + neg => ELECTRICAL_REF + ); + + R2 : entity work.resistor(ideal) + generic map( + res => 10.0e3 + ) + port map( + p1 => sin_out2, + p2 => electrical_ref + ); +end TB_v_source ; + + diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/v_source-1.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/v_source-1.vhd new file mode 100644 index 000000000..46264eb5a --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/v_source-1.vhd @@ -0,0 +1,58 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee; use ieee.math_real.all; +library ieee_proposed; use ieee_proposed.electrical_systems.all; + +entity v_source is + generic ( DC : voltage := 1.0; -- output peak amplitude + min_freq : real := 10.0; -- minimum frequency for spectral source + max_freq : real := 1.0e4; -- maximum frequency for spectral source + ac_mag : voltage := 1.0; -- AC magnitude + ac_phase : real := 0.0 ); -- AC phase [degree] + port ( terminal pos, neg : electrical ); +end entity v_source; + +---------------------------------------------------------------- + +architecture behavior of v_source is + + function g (freq : real) return real is + begin + if (freq > min_freq and freq < max_freq) then + return 1.0; + else + return 0.0; + end if; + end function g; + + quantity vout across iout through pos to neg; + -- declare quantity in frequency domain for AC analysis + quantity ac_spec : real spectrum ac_mag*g(frequency), + math_2_pi*ac_phase/360.0; + +begin + + if domain = quiescent_domain or domain = time_domain use + vout == DC; + else + vout == ac_spec; -- used for frequency (AC) analysis + end use; + +end architecture behavior; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/v_source.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/v_source.vhd new file mode 100644 index 000000000..c8f12e01d --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/v_source.vhd @@ -0,0 +1,46 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee; use ieee.math_real.all; +library ieee_proposed; use ieee_proposed.electrical_systems.all; + +entity v_source is + generic ( DC : voltage := 1.0; -- output peak amplitude + ac_mag : voltage := 1.0; -- AC magnitude + ac_phase : real := 0.0 ); -- AC phase [degree] + port ( terminal pos, neg : electrical ); +end entity v_source; + +---------------------------------------------------------------- + +architecture behavior of v_source is + + quantity vout across iout through pos to neg; + -- declare quantity in frequency domain for AC analysis + quantity ac_spec : real spectrum ac_mag, math_2_pi*ac_phase/360.0; + +begin + + if domain = quiescent_domain or domain = time_domain use + vout == DC; + else + vout == ac_spec; -- used for frequency (AC) analysis + end use; + +end architecture behavior; |