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Diffstat (limited to 'testsuite/synth/issue2042/ent3.vhdl')
-rw-r--r-- | testsuite/synth/issue2042/ent3.vhdl | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/testsuite/synth/issue2042/ent3.vhdl b/testsuite/synth/issue2042/ent3.vhdl new file mode 100644 index 000000000..e54e4f41b --- /dev/null +++ b/testsuite/synth/issue2042/ent3.vhdl @@ -0,0 +1,32 @@ +library IEEE; +use IEEE.std_logic_1164.ALL; +use IEEE.numeric_std.all; + +entity ent is + generic ( + g_NumberOfChannels : natural := 4; + g_BitsPerChannel : natural := 16 + ); + port ( + CLK : in std_logic; + RST : in std_logic + ); +end entity; + +architecture arch of ent is + + signal do_out : STD_LOGIC_VECTOR(15 DOWNTO 0); + +begin + + process(RST, CLK) + variable cnt: natural range 0 to g_NumberOfChannels-1; + begin + if RST then + cnt := 0; + elsif rising_edge(CLK) then + cnt := cnt + 1 when cnt<g_NumberOfChannels-1 else 0; + end if; + end process; + +end architecture; |