diff options
-rw-r--r-- | testsuite/synth/issue2042/ent.vhdl | 34 | ||||
-rw-r--r-- | testsuite/synth/issue2042/ent1.vhdl | 34 | ||||
-rw-r--r-- | testsuite/synth/issue2042/ent3.vhdl | 32 | ||||
-rwxr-xr-x | testsuite/synth/issue2042/testsuite.sh | 8 |
4 files changed, 108 insertions, 0 deletions
diff --git a/testsuite/synth/issue2042/ent.vhdl b/testsuite/synth/issue2042/ent.vhdl new file mode 100644 index 000000000..5e8727a60 --- /dev/null +++ b/testsuite/synth/issue2042/ent.vhdl @@ -0,0 +1,34 @@ +library IEEE; +use IEEE.std_logic_1164.ALL; +use IEEE.numeric_std.all; + +entity ent is + generic ( + g_NumberOfChannels : natural := 4; + g_BitsPerChannel : natural := 16 + ); + port ( + CLK : in std_logic; + RST : in std_logic; + DATA : out std_logic_vector(g_NumberOfChannels*g_BitsPerChannel-1 downto 0) + ); +end entity; + +architecture arch of ent is + + signal do_out : STD_LOGIC_VECTOR(15 DOWNTO 0); + +begin + + process(RST, CLK) + variable cnt: natural range 0 to g_NumberOfChannels-1; + begin + if RST then + cnt := 0; + elsif rising_edge(CLK) then + DATA((cnt+1)*g_BitsPerChannel-1 downto cnt*g_BitsPerChannel) <= do_out(do_out'left downto 1+do_out'left-g_BitsPerChannel); + cnt := cnt + 1 when cnt<g_NumberOfChannels-1 else 0; + end if; + end process; + +end architecture; diff --git a/testsuite/synth/issue2042/ent1.vhdl b/testsuite/synth/issue2042/ent1.vhdl new file mode 100644 index 000000000..0225e9023 --- /dev/null +++ b/testsuite/synth/issue2042/ent1.vhdl @@ -0,0 +1,34 @@ +library IEEE; +use IEEE.std_logic_1164.ALL; +use IEEE.numeric_std.all; + +entity ent is + generic ( + g_NumberOfChannels : natural := 4; + g_BitsPerChannel : natural := 16 + ); + port ( + CLK : in std_logic; + RST : in std_logic; + DATA : out std_logic_vector(g_NumberOfChannels*g_BitsPerChannel-1 downto 0) + ); +end entity; + +architecture arch of ent is + + signal do_out : STD_LOGIC_VECTOR(15 DOWNTO 0); + +begin + + process(RST, CLK) + variable cnt: natural range 0 to g_NumberOfChannels-1; + begin + if RST then + cnt := 0; + elsif rising_edge(CLK) then + DATA((cnt+1)*g_BitsPerChannel-1 downto cnt*g_BitsPerChannel) <= do_out(do_out'left downto do_out'left-g_BitsPerChannel+1); + -- cnt := cnt + 1 when cnt<g_NumberOfChannels-1 else 0; + end if; + end process; + +end architecture; diff --git a/testsuite/synth/issue2042/ent3.vhdl b/testsuite/synth/issue2042/ent3.vhdl new file mode 100644 index 000000000..e54e4f41b --- /dev/null +++ b/testsuite/synth/issue2042/ent3.vhdl @@ -0,0 +1,32 @@ +library IEEE; +use IEEE.std_logic_1164.ALL; +use IEEE.numeric_std.all; + +entity ent is + generic ( + g_NumberOfChannels : natural := 4; + g_BitsPerChannel : natural := 16 + ); + port ( + CLK : in std_logic; + RST : in std_logic + ); +end entity; + +architecture arch of ent is + + signal do_out : STD_LOGIC_VECTOR(15 DOWNTO 0); + +begin + + process(RST, CLK) + variable cnt: natural range 0 to g_NumberOfChannels-1; + begin + if RST then + cnt := 0; + elsif rising_edge(CLK) then + cnt := cnt + 1 when cnt<g_NumberOfChannels-1 else 0; + end if; + end process; + +end architecture; diff --git a/testsuite/synth/issue2042/testsuite.sh b/testsuite/synth/issue2042/testsuite.sh new file mode 100755 index 000000000..c06b922b8 --- /dev/null +++ b/testsuite/synth/issue2042/testsuite.sh @@ -0,0 +1,8 @@ +#! /bin/sh + +. ../../testenv.sh + +GHDL_STD_FLAGS=--std=08 +synth_only ent3 + +echo "Test successful" |