1 files changed, 23 insertions, 0 deletions
diff --git a/testsuite/synth/issue1414/cover_overlap_misparse.vhdl b/testsuite/synth/issue1414/cover_overlap_misparse.vhdl
new file mode 100644
index 000000000..895bcf715
--- /dev/null
+++ b/testsuite/synth/issue1414/cover_overlap_misparse.vhdl
@@ -0,0 +1,23 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+entity cover_overlap_misparse is
+    Port (
+        clk: in STD_LOGIC;
+        counter_val: out STD_LOGIC_VECTOR(3 downto 0)
+    );
+end entity;
+
+architecture Behavioral of cover_overlap_misparse is
+    signal ctr_internal: UNSIGNED(3 downto 0) := x"0";
+begin
+    process(clk) is
+    begin
+        ctr_internal <= ctr_internal + 1;
+    end process;
+    counter_val <= STD_LOGIC_VECTOR(ctr_internal);
+
+    -- psl default clock is rising_edge(clk);
+    --psl assert always ctr_internal = 0 |-> ctr_internal = 0;
+end Behavioral;