diff options
Diffstat (limited to 'testsuite/pyunit/dom')
-rw-r--r-- | testsuite/pyunit/dom/Simple.py (renamed from testsuite/pyunit/dom/SimpleEntity.py) | 51 | ||||
-rw-r--r-- | testsuite/pyunit/dom/examples/SimpleEntity.vhdl | 55 | ||||
-rw-r--r-- | testsuite/pyunit/dom/examples/SimplePackage.vhdl | 28 |
3 files changed, 133 insertions, 1 deletions
diff --git a/testsuite/pyunit/dom/SimpleEntity.py b/testsuite/pyunit/dom/Simple.py index c2167c973..32033609d 100644 --- a/testsuite/pyunit/dom/SimpleEntity.py +++ b/testsuite/pyunit/dom/Simple.py @@ -44,7 +44,7 @@ if __name__ == "__main__": class SimpleEntity(TestCase): _root = Path(__file__).resolve().parent.parent - _filename: Path = _root / "SimpleEntity.vhdl" + _filename: Path = _root / "dom/examples/SimpleEntity.vhdl" def test_Design(self): design = Design() @@ -89,3 +89,52 @@ class SimpleEntity(TestCase): print() print(architecture.Documentation) self.assertEqual(1, len(architecture.Documentation.splitlines())) + + +class SimplePackage(TestCase): + _root = Path(__file__).resolve().parent.parent + _filename: Path = _root / "dom/examples/SimplePackage.vhdl" + + def test_Design(self): + design = Design() + + self.assertIsNotNone(design) + + # def test_Library(self): + # library = Library() + + def test_Document(self): + design = Design() + document = Document(self._filename) + design.Documents.append(document) + + self.assertEqual(1, len(design.Documents)) + print() + print(document.Documentation) + self.assertEqual(4, len(document.Documentation.splitlines())) + + def test_Package(self): + design = Design() + document = Document(self._filename) + design.Documents.append(document) + + self.assertEqual(1, len(design.Documents[0].Packages)) + + package = design.Documents[0].Packages[0] + self.assertEqual("utilities", package.Identifier) + print() + print(package.Documentation) + self.assertEqual(1, len(package.Documentation.splitlines())) + + def test_PackageBody(self): + design = Design() + document = Document(self._filename) + design.Documents.append(document) + + self.assertEqual(1, len(design.Documents[0].PackageBodies)) + + packageBodies = design.Documents[0].PackageBodies[0] + self.assertEqual("utilities", packageBodies.Identifier) + print() + print(packageBodies.Documentation) + self.assertEqual(0, len(packageBodies.Documentation.splitlines())) diff --git a/testsuite/pyunit/dom/examples/SimpleEntity.vhdl b/testsuite/pyunit/dom/examples/SimpleEntity.vhdl new file mode 100644 index 000000000..bdeae47e1 --- /dev/null +++ b/testsuite/pyunit/dom/examples/SimpleEntity.vhdl @@ -0,0 +1,55 @@ +-- Author: Patrick Lehmann +-- +-- A generic counter module used in the StopWatch example. +-- +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +use work.Utilities.all; + +-- Generic modulo N counter +-- +-- This component implements a generic modulo N counter with synchronous reset +-- and enable. It generates a wrap-around strobe signal when it roles from +-- MODULO-1 back to zero. +-- +-- .. hint:: +-- +-- A modulo N counter counts binary from zero to N-1. +-- +-- This component uses VHDL-2008 features like readback of ``out`` ports. +entity Counter is + generic ( + MODULO : positive; -- Modulo value. + BITS : natural := log2(MODULO) -- Number of expected output bits. + ); + port ( + Clock : in std_logic; -- Component clock + Reset : in std_logic; -- Component reset (synchronous) + Enable : in std_logic; -- Component enable (synchronous) + + Value : out unsigned(BITS - 1 downto 0); -- Current counter value + WrapAround : out std_logic -- Strobe output on change from MODULO-1 to zero + ); +end entity; + + +-- Synthesizable and simulatable variant of a generic counter. +architecture rtl of Counter is + signal CounterValue : unsigned(log2(MODULO) - 1 downto 0) := (others => '0'); +begin + process (Clock) + begin + if rising_edge(Clock) then + if ((Reset or WrapAround) = '1') then + CounterValue <= (others => '0'); + elsif (Enable = '1') then + CounterValue <= CounterValue + 1; + end if; + end if; + end process; + + Value <= resize(CounterValue, BITS); + WrapAround <= Enable when (CounterValue = MODULO - 1) else '0'; +end architecture; diff --git a/testsuite/pyunit/dom/examples/SimplePackage.vhdl b/testsuite/pyunit/dom/examples/SimplePackage.vhdl new file mode 100644 index 000000000..04df1c521 --- /dev/null +++ b/testsuite/pyunit/dom/examples/SimplePackage.vhdl @@ -0,0 +1,28 @@ +-- Author: Patrick Lehmann +-- +-- A collection of utility types and functions. +-- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +-- Utility package +package utilities is + -- Deferred constant to distinguish simulation from synthesis. + constant IS_SIMULATION : boolean; + +end package; + +package body utilities is + function simulation return boolean is + variable result : boolean := false; + begin + -- synthesis translate off + result := true; + -- synthesis translate on + return result; + end function; + + constant IS_SIMULATION : boolean := simulation; + +end package body; |