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-rw-r--r--testsuite/pyunit/SimpleEntity.vhdl4
1 files changed, 2 insertions, 2 deletions
diff --git a/testsuite/pyunit/SimpleEntity.vhdl b/testsuite/pyunit/SimpleEntity.vhdl
index 90d68fd83..931599086 100644
--- a/testsuite/pyunit/SimpleEntity.vhdl
+++ b/testsuite/pyunit/SimpleEntity.vhdl
@@ -4,7 +4,7 @@ use ieee.numeric_std.all;
entity entity_1 is
generic (
- FREQ : real := 100.0;
+ FREQ : real := (100.0 * 1024.0 * 1024.0);
BITS : positive := 8
);
port (
@@ -17,7 +17,7 @@ end entity entity_1;
architecture behav of entity_1 is
signal Reset_n : std_logic;
begin
- Reset_n <= not Reset;
+ Reset_n <= (not Reset);
process(Clock)
begin