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-rw-r--r--pyGHDL/dom/Expression.py15
-rw-r--r--pyGHDL/dom/Misc.py4
-rw-r--r--pyGHDL/dom/_Translate.py2
-rw-r--r--pyGHDL/dom/formatting/prettyprint.py36
-rw-r--r--testsuite/pyunit/SimpleEntity.vhdl4
5 files changed, 43 insertions, 18 deletions
diff --git a/pyGHDL/dom/Expression.py b/pyGHDL/dom/Expression.py
index a6b88ac23..fec347b57 100644
--- a/pyGHDL/dom/Expression.py
+++ b/pyGHDL/dom/Expression.py
@@ -52,6 +52,7 @@ from pyVHDLModel.VHDLModel import (
IdentityExpression as VHDLModel_IdentityExpression,
NegationExpression as VHDLModel_NegationExpression,
AbsoluteExpression as VHDLModel_AbsoluteExpression,
+ ParenthesisExpression as VHDLModel_ParenthesisExpression,
TypeConversion as VHDLModel_TypeConversion,
FunctionCall as VHDLModel_FunctionCall,
QualifiedExpression as VHDLModel_QualifiedExpression,
@@ -136,6 +137,20 @@ class AbsoluteExpression(VHDLModel_AbsoluteExpression, _ParseUnaryExpression):
@export
+class ParenthesisExpression(VHDLModel_ParenthesisExpression, _ParseUnaryExpression):
+ def __init__(self, operand: Expression):
+ super().__init__()
+ self._operand = operand
+
+ @classmethod
+ def parse(cls, node):
+ from pyGHDL.dom._Translate import GetExpressionFromNode
+
+ operand = GetExpressionFromNode(nodes.Get_Expression(node))
+ return cls(operand)
+
+
+@export
class TypeConversion(VHDLModel_TypeConversion):
def __init__(self, operand: Expression):
super().__init__()
diff --git a/pyGHDL/dom/Misc.py b/pyGHDL/dom/Misc.py
index 6ef66fcf0..7bee2ec7b 100644
--- a/pyGHDL/dom/Misc.py
+++ b/pyGHDL/dom/Misc.py
@@ -52,7 +52,7 @@ from pyGHDL.libghdl import (
LibGHDLException,
utils,
)
-from pyGHDL.libghdl.vhdl import nodes, sem_lib
+from pyGHDL.libghdl.vhdl import nodes, sem_lib, parse
from pyGHDL.dom._Utils import GetIirKindOfNode
from pyGHDL.dom.Common import DOMException, GHDLMixin
@@ -86,6 +86,8 @@ class Design(VHDLModel_Design):
libghdl.set_option("--std=08")
+ parse.Flag_Parse_Parenthesis.value = True
+
# Finish initialization. This will load the standard package.
if libghdl.analyze_init_status() != 0:
raise LibGHDLException("Error initializing 'libghdl'.")
diff --git a/pyGHDL/dom/_Translate.py b/pyGHDL/dom/_Translate.py
index 8a4a717e9..24f056f33 100644
--- a/pyGHDL/dom/_Translate.py
+++ b/pyGHDL/dom/_Translate.py
@@ -56,6 +56,7 @@ from pyGHDL.dom.Expression import (
ExponentiationExpression,
Aggregate,
NegationExpression,
+ ParenthesisExpression,
)
__all__ = []
@@ -134,6 +135,7 @@ __EXPRESSION_TRANSLATION = {
nodes.Iir_Kind.Negation_Operator: NegationExpression,
nodes.Iir_Kind.Addition_Operator: AdditionExpression,
nodes.Iir_Kind.Not_Operator: InverseExpression,
+ nodes.Iir_Kind.Parenthesis_Expression: ParenthesisExpression,
nodes.Iir_Kind.Substraction_Operator: SubtractionExpression,
nodes.Iir_Kind.Multiplication_Operator: MultiplyExpression,
nodes.Iir_Kind.Division_Operator: DivisionExpression,
diff --git a/pyGHDL/dom/formatting/prettyprint.py b/pyGHDL/dom/formatting/prettyprint.py
index 8ee49275c..c10b7cf87 100644
--- a/pyGHDL/dom/formatting/prettyprint.py
+++ b/pyGHDL/dom/formatting/prettyprint.py
@@ -48,6 +48,7 @@ from pyGHDL.dom.Expression import (
NegationExpression,
ExponentiationExpression,
Aggregate,
+ ParenthesisExpression,
)
from pyGHDL.dom.Aggregates import (
SimpleAggregateElement,
@@ -70,18 +71,19 @@ ModeTranslation = {
}
UnaryExpressionTranslation = {
- IdentityExpression: " +",
- NegationExpression: " -",
- InverseExpression: "not ",
- AbsoluteExpression: "abs ",
+ IdentityExpression: (" +", ""),
+ NegationExpression: (" -", ""),
+ InverseExpression: ("not ", ""),
+ AbsoluteExpression: ("abs ", ""),
+ ParenthesisExpression: ("(", ")"),
}
BinaryExpressionTranslation = {
- AdditionExpression: " + ",
- SubtractionExpression: " - ",
- MultiplyExpression: " * ",
- DivisionExpression: " / ",
- ExponentiationExpression: "**",
+ AdditionExpression: ("", " + ", ""),
+ SubtractionExpression: ("", " - ", ""),
+ MultiplyExpression: ("", " * ", ""),
+ DivisionExpression: ("", " / ", ""),
+ ExponentiationExpression: ("", "**", ""),
}
@@ -401,8 +403,10 @@ class PrettyPrint:
except KeyError:
raise PrettyPrintException("Unhandled operator for unary expression.")
- return "{operator}{operand}".format(
- operand=self.formatExpression(expression.Operand), operator=operator
+ return "{leftOp}{operand}{rightOp}".format(
+ leftOp=operator[0],
+ rightOp=operator[1],
+ operand=self.formatExpression(expression.Operand),
)
elif isinstance(expression, BinaryExpression):
try:
@@ -410,10 +414,12 @@ class PrettyPrint:
except KeyError:
raise PrettyPrintException("Unhandled operator for binary expression.")
- return "{left}{operator}{right}".format(
- left=self.formatExpression(expression.LeftOperand),
- right=self.formatExpression(expression.RightOperand),
- operator=operator,
+ return "{leftOp}{leftExpr}{middleOp}{rightExpr}{rightOp}".format(
+ leftOp=operator[0],
+ middleOp=operator[1],
+ rightOp=operator[2],
+ leftExpr=self.formatExpression(expression.LeftOperand),
+ rightExpr=self.formatExpression(expression.RightOperand),
)
elif isinstance(expression, Aggregate):
return "({choices})".format(
diff --git a/testsuite/pyunit/SimpleEntity.vhdl b/testsuite/pyunit/SimpleEntity.vhdl
index 90d68fd83..931599086 100644
--- a/testsuite/pyunit/SimpleEntity.vhdl
+++ b/testsuite/pyunit/SimpleEntity.vhdl
@@ -4,7 +4,7 @@ use ieee.numeric_std.all;
entity entity_1 is
generic (
- FREQ : real := 100.0;
+ FREQ : real := (100.0 * 1024.0 * 1024.0);
BITS : positive := 8
);
port (
@@ -17,7 +17,7 @@ end entity entity_1;
architecture behav of entity_1 is
signal Reset_n : std_logic;
begin
- Reset_n <= not Reset;
+ Reset_n <= (not Reset);
process(Clock)
begin