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-rw-r--r--testsuite/gna/issue264/ex1_top.vhdl24
-rwxr-xr-xtestsuite/gna/issue264/testsuite.sh7
2 files changed, 31 insertions, 0 deletions
diff --git a/testsuite/gna/issue264/ex1_top.vhdl b/testsuite/gna/issue264/ex1_top.vhdl
new file mode 100644
index 000000000..c7a268b71
--- /dev/null
+++ b/testsuite/gna/issue264/ex1_top.vhdl
@@ -0,0 +1,24 @@
+entity ex1_entity is
+ port (
+ X : inout boolean -- std_logic works
+ );
+end entity;
+
+architecture a of ex1_entity is
+begin
+end architecture;
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity ex1_top is
+end entity;
+
+architecture a of ex1_top is
+ signal A : std_logic;
+begin
+ inst : entity work.ex1_entity
+ port map (
+ X => A -- line containing error
+ );
+end architecture;
diff --git a/testsuite/gna/issue264/testsuite.sh b/testsuite/gna/issue264/testsuite.sh
new file mode 100755
index 000000000..f3b73761f
--- /dev/null
+++ b/testsuite/gna/issue264/testsuite.sh
@@ -0,0 +1,7 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+analyze_failure ex1_top.vhdl
+
+echo "Test successful"