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Diffstat (limited to 'testsuite/gna/issue2421/top.vhdl')
-rw-r--r-- | testsuite/gna/issue2421/top.vhdl | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/testsuite/gna/issue2421/top.vhdl b/testsuite/gna/issue2421/top.vhdl new file mode 100644 index 000000000..676e57efd --- /dev/null +++ b/testsuite/gna/issue2421/top.vhdl @@ -0,0 +1,31 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity comp is + port ( + output : out std_logic_vector + ); +end entity; + +architecture a1 of comp is +begin + output <= (others => '0'); + -- output <= (output'range => '0'); -- gives no error +end architecture; + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity top is +end entity; + +architecture a2 of top is + signal sig : std_logic_vector(7 downto 0); +begin + inst : entity work.comp + port map ( + output => sig + ); +end architecture; |