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-rw-r--r--testsuite/gna/issue2116/attr4.vhdl4
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diff --git a/testsuite/gna/issue2116/attr4.vhdl b/testsuite/gna/issue2116/attr4.vhdl
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+library ieee;use ieee.std_logic_1164;entity d is
+port(s:std'r);end entity;architecture c of t is
+begin
+t;end architecture; \ No newline at end of file