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-rw-r--r--testsuite/gna/issue2116/attr17.vhdl6
1 files changed, 6 insertions, 0 deletions
diff --git a/testsuite/gna/issue2116/attr17.vhdl b/testsuite/gna/issue2116/attr17.vhdl
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+++ b/testsuite/gna/issue2116/attr17.vhdl
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+library ieee;use ieee.std_logic_1164;use ieee.numeric_std.all;entity hello is
+port(c:std'l;t:d(0));end hello;architecture behav of h is
+signal v:d(0);begin
+process(l)begin
+if(0)then if'0'then
+v<=0;end if;end if;end process;end behav; \ No newline at end of file