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-rw-r--r--testsuite/gna/issue2116/attr15.vhdl6
1 files changed, 6 insertions, 0 deletions
diff --git a/testsuite/gna/issue2116/attr15.vhdl b/testsuite/gna/issue2116/attr15.vhdl
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+++ b/testsuite/gna/issue2116/attr15.vhdl
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+library ieee;use ieee.std_logic_1164;entity t is
+port(s:std'l);end entity;architecture a of t is
+begin i;end architecture;library i;entity b is
+end entity;architecture h of b is
+signal n:r(0);signal s:s(0);begin process begin
+end process;t(0);end architecture; \ No newline at end of file