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-rw-r--r--src/vhdl/configuration.adb16
-rw-r--r--src/vhdl/ieee-vital_timing.adb16
-rw-r--r--src/vhdl/post_sems.adb4
-rw-r--r--src/vhdl/simulate/simul-debugger.adb14
-rw-r--r--src/vhdl/simulate/simul-elaboration.adb2
-rw-r--r--src/vhdl/simulate/simul-execution.adb6
-rw-r--r--src/vhdl/std_package.adb12
-rw-r--r--src/vhdl/translate/ortho_front.adb6
-rw-r--r--src/vhdl/translate/trans-chap12.adb6
-rw-r--r--src/vhdl/translate/trans-chap2.adb6
-rw-r--r--src/vhdl/translate/translation.adb4
-rw-r--r--src/vhdl/vhdl-canon.adb6
-rw-r--r--src/vhdl/vhdl-sem.adb (renamed from src/vhdl/sem.adb)24
-rw-r--r--src/vhdl/vhdl-sem.ads (renamed from src/vhdl/sem.ads)4
-rw-r--r--src/vhdl/vhdl-sem_assocs.adb (renamed from src/vhdl/sem_assocs.adb)12
-rw-r--r--src/vhdl/vhdl-sem_assocs.ads (renamed from src/vhdl/sem_assocs.ads)6
-rw-r--r--src/vhdl/vhdl-sem_decls.adb (renamed from src/vhdl/sem_decls.adb)22
-rw-r--r--src/vhdl/vhdl-sem_decls.ads (renamed from src/vhdl/sem_decls.ads)4
-rw-r--r--src/vhdl/vhdl-sem_expr.adb (renamed from src/vhdl/sem_expr.adb)18
-rw-r--r--src/vhdl/vhdl-sem_expr.ads (renamed from src/vhdl/sem_expr.ads)4
-rw-r--r--src/vhdl/vhdl-sem_inst.adb (renamed from src/vhdl/sem_inst.adb)6
-rw-r--r--src/vhdl/vhdl-sem_inst.ads (renamed from src/vhdl/sem_inst.ads)4
-rw-r--r--src/vhdl/vhdl-sem_lib.adb (renamed from src/vhdl/sem_lib.adb)6
-rw-r--r--src/vhdl/vhdl-sem_lib.ads (renamed from src/vhdl/sem_lib.ads)4
-rw-r--r--src/vhdl/vhdl-sem_names.adb (renamed from src/vhdl/sem_names.adb)24
-rw-r--r--src/vhdl/vhdl-sem_names.ads (renamed from src/vhdl/sem_names.ads)4
-rw-r--r--src/vhdl/vhdl-sem_psl.adb (renamed from src/vhdl/sem_psl.adb)12
-rw-r--r--src/vhdl/vhdl-sem_psl.ads (renamed from src/vhdl/sem_psl.ads)4
-rw-r--r--src/vhdl/vhdl-sem_scopes.adb (renamed from src/vhdl/sem_scopes.adb)4
-rw-r--r--src/vhdl/vhdl-sem_scopes.ads (renamed from src/vhdl/sem_scopes.ads)4
-rw-r--r--src/vhdl/vhdl-sem_specs.adb (renamed from src/vhdl/sem_specs.adb)18
-rw-r--r--src/vhdl/vhdl-sem_specs.ads (renamed from src/vhdl/sem_specs.ads)4
-rw-r--r--src/vhdl/vhdl-sem_stmts.adb (renamed from src/vhdl/sem_stmts.adb)20
-rw-r--r--src/vhdl/vhdl-sem_stmts.ads (renamed from src/vhdl/sem_stmts.ads)4
-rw-r--r--src/vhdl/vhdl-sem_types.adb (renamed from src/vhdl/sem_types.adb)16
-rw-r--r--src/vhdl/vhdl-sem_types.ads (renamed from src/vhdl/sem_types.ads)4
-rw-r--r--src/vhdl/vhdl-sem_utils.adb (renamed from src/vhdl/sem_utils.adb)4
-rw-r--r--src/vhdl/vhdl-sem_utils.ads (renamed from src/vhdl/sem_utils.ads)4
38 files changed, 169 insertions, 169 deletions
diff --git a/src/vhdl/configuration.adb b/src/vhdl/configuration.adb
index fd8a72605..d047da43d 100644
--- a/src/vhdl/configuration.adb
+++ b/src/vhdl/configuration.adb
@@ -23,8 +23,8 @@ with Name_Table; use Name_Table;
with Flags;
with Iirs_Utils; use Iirs_Utils;
with Iirs_Walk;
-with Sem_Scopes;
-with Sem_Lib; use Sem_Lib;
+with Vhdl.Sem_Scopes;
+with Vhdl.Sem_Lib; use Vhdl.Sem_Lib;
with Vhdl.Canon;
package body Configuration is
@@ -803,7 +803,7 @@ package body Configuration is
Load_Design_Unit (Design, Null_Iir);
when Iir_Kind_Entity_Declaration =>
Load_Design_Unit (Design, Null_Iir);
- Sem_Scopes.Add_Name (Get_Library_Unit (Design));
+ Vhdl.Sem_Scopes.Add_Name (Get_Library_Unit (Design));
when Iir_Kind_Package_Declaration
| Iir_Kind_Package_Instantiation_Declaration
| Iir_Kind_Package_Body
@@ -851,7 +851,7 @@ package body Configuration is
end if;
end;
declare
- use Sem_Scopes;
+ use Vhdl.Sem_Scopes;
Comp : constant Iir := Get_Named_Entity (Inst);
Interp : constant Name_Interpretation_Type :=
Get_Interpretation (Get_Identifier (Comp));
@@ -913,8 +913,8 @@ package body Configuration is
Status : Walk_Status;
begin
-- Name table is used to map names to entities.
- Sem_Scopes.Push_Interpretations;
- Sem_Scopes.Open_Declarative_Region;
+ Vhdl.Sem_Scopes.Push_Interpretations;
+ Vhdl.Sem_Scopes.Open_Declarative_Region;
-- 1. Add all design entities in the name table.
Status := Walk_Design_Units (Lib, Add_Entity_Cb'Access);
@@ -925,8 +925,8 @@ package body Configuration is
Status := Walk_Design_Units (Lib, Mark_Units_Cb'Access);
pragma Assert (Status = Walk_Continue);
- Sem_Scopes.Close_Declarative_Region;
- Sem_Scopes.Pop_Interpretations;
+ Vhdl.Sem_Scopes.Close_Declarative_Region;
+ Vhdl.Sem_Scopes.Pop_Interpretations;
end Mark_Instantiated_Units;
function Extract_Entity_Cb (Design : Iir) return Walk_Status
diff --git a/src/vhdl/ieee-vital_timing.adb b/src/vhdl/ieee-vital_timing.adb
index ee60bbd15..a1413285e 100644
--- a/src/vhdl/ieee-vital_timing.adb
+++ b/src/vhdl/ieee-vital_timing.adb
@@ -22,10 +22,10 @@ with Std_Package; use Std_Package;
with Vhdl.Tokens; use Vhdl.Tokens;
with Name_Table;
with Ieee.Std_Logic_1164; use Ieee.Std_Logic_1164;
-with Sem_Scopes;
-with Sem_Specs;
+with Vhdl.Sem_Scopes;
+with Vhdl.Sem_Specs;
with Evaluation;
-with Sem;
+with Vhdl.Sem;
with Iirs_Utils;
package body Ieee.Vital_Timing is
@@ -317,7 +317,7 @@ package body Ieee.Vital_Timing is
-- Returns the port.
function Check_Port return Iir
is
- use Sem_Scopes;
+ use Vhdl.Sem_Scopes;
use Name_Table;
C : Character;
@@ -1052,8 +1052,8 @@ package body Ieee.Vital_Timing is
-- Furthermore, the type of the biased propagation generic
-- shall be the same as the type of the corresponding delay
-- generic.
- if not Sem.Are_Trees_Equal (Get_Type (Decl),
- Get_Type (Tpd_Decl))
+ if not Vhdl.Sem.Are_Trees_Equal (Get_Type (Decl),
+ Get_Type (Tpd_Decl))
then
Error_Vital
(+Decl, "type of VITAL 'tbpd' generic mismatch type of "
@@ -1241,7 +1241,7 @@ package body Ieee.Vital_Timing is
-- Checks rules for a VITAL level 0 entity.
procedure Check_Vital_Level0_Entity (Ent : Iir_Entity_Declaration)
is
- use Sem_Scopes;
+ use Vhdl.Sem_Scopes;
Decl : Iir;
Gen_Chain : Iir;
begin
@@ -1295,7 +1295,7 @@ package body Ieee.Vital_Timing is
Value : Iir_Attribute_Value;
Spec : Iir_Attribute_Specification;
begin
- Value := Sem_Specs.Find_Attribute_Value
+ Value := Vhdl.Sem_Specs.Find_Attribute_Value
(Unit, Std_Names.Name_VITAL_Level0);
if Value = Null_Iir then
return False;
diff --git a/src/vhdl/post_sems.adb b/src/vhdl/post_sems.adb
index 43e8ec76f..d00a808c0 100644
--- a/src/vhdl/post_sems.adb
+++ b/src/vhdl/post_sems.adb
@@ -17,7 +17,7 @@
-- 02111-1307, USA.
with Types; use Types;
with Std_Names; use Std_Names;
-with Sem_Specs;
+with Vhdl.Sem_Specs;
with Ieee.Std_Logic_1164;
with Ieee.Vital_Timing;
with Ieee.Numeric;
@@ -65,7 +65,7 @@ package body Post_Sems is
-- Look for VITAL attributes.
if Flag_Vital_Checks then
Value := Get_Attribute_Value_Chain
- (Sem_Specs.Get_Attribute_Value_Chain_Parent (Lib_Unit));
+ (Vhdl.Sem_Specs.Get_Attribute_Value_Chain_Parent (Lib_Unit));
while Value /= Null_Iir loop
Spec := Get_Attribute_Specification (Value);
Attr_Decl := Get_Named_Entity (Get_Attribute_Designator (Spec));
diff --git a/src/vhdl/simulate/simul-debugger.adb b/src/vhdl/simulate/simul-debugger.adb
index 10789cb25..8c911a706 100644
--- a/src/vhdl/simulate/simul-debugger.adb
+++ b/src/vhdl/simulate/simul-debugger.adb
@@ -26,8 +26,8 @@ with Files_Map;
with Vhdl.Parse;
with Vhdl.Scanner;
with Vhdl.Tokens;
-with Sem_Expr;
-with Sem_Scopes;
+with Vhdl.Sem_Expr;
+with Vhdl.Sem_Scopes;
with Vhdl.Canon;
with Std_Names;
with Libraries;
@@ -1750,7 +1750,7 @@ package body Simul.Debugger is
procedure Add_Decls_For (N : Iir)
is
- use Sem_Scopes;
+ use Vhdl.Sem_Scopes;
begin
case Get_Kind (N) is
when Iir_Kind_Entity_Declaration =>
@@ -1819,7 +1819,7 @@ package body Simul.Debugger is
procedure Enter_Scope (Node : Iir)
is
- use Sem_Scopes;
+ use Vhdl.Sem_Scopes;
begin
Push_Interpretations;
Open_Declarative_Region;
@@ -1833,7 +1833,7 @@ package body Simul.Debugger is
procedure Del_Decls_For (N : Iir)
is
- use Sem_Scopes;
+ use Vhdl.Sem_Scopes;
begin
case Get_Kind (N) is
when Iir_Kind_Entity_Declaration =>
@@ -1858,7 +1858,7 @@ package body Simul.Debugger is
procedure Leave_Scope (Node : Iir)
is
- use Sem_Scopes;
+ use Vhdl.Sem_Scopes;
begin
Foreach_Scopes (Node, Del_Decls_For'Access);
@@ -1914,7 +1914,7 @@ package body Simul.Debugger is
end if;
Enter_Scope (Dbg_Cur_Frame.Stmt);
- Expr := Sem_Expr.Sem_Expression_Universal (Expr);
+ Expr := Vhdl.Sem_Expr.Sem_Expression_Universal (Expr);
Leave_Scope (Dbg_Cur_Frame.Stmt);
if Expr = Null_Iir
diff --git a/src/vhdl/simulate/simul-elaboration.adb b/src/vhdl/simulate/simul-elaboration.adb
index cb9c8cb9b..3addbef91 100644
--- a/src/vhdl/simulate/simul-elaboration.adb
+++ b/src/vhdl/simulate/simul-elaboration.adb
@@ -26,7 +26,7 @@ with Libraries;
with Name_Table;
with Simul.File_Operation;
with Iir_Chains; use Iir_Chains;
-with Sem_Lib; use Sem_Lib;
+with Vhdl.Sem_Lib; use Vhdl.Sem_Lib;
with Simul.Annotations; use Simul.Annotations;
with Simul.Elaboration.AMS; use Simul.Elaboration.AMS;
with Areapools; use Areapools;
diff --git a/src/vhdl/simulate/simul-execution.adb b/src/vhdl/simulate/simul-execution.adb
index f034bb9b6..3a1c11028 100644
--- a/src/vhdl/simulate/simul-execution.adb
+++ b/src/vhdl/simulate/simul-execution.adb
@@ -44,7 +44,7 @@ with Grt.Errors;
with Grt.Std_Logic_1164;
with Grt.Lib;
with Grt.Strings;
-with Sem_Inst;
+with Vhdl.Sem_Inst;
package body Simul.Execution is
@@ -3344,7 +3344,7 @@ package body Simul.Execution is
if Res /= Null_Iir then
return Res;
else
- Orig := Sem_Inst.Get_Origin (Spec);
+ Orig := Vhdl.Sem_Inst.Get_Origin (Spec);
pragma Assert (Orig /= Null_Iir);
return Get_Subprogram_Body_Origin (Orig);
end if;
@@ -3361,7 +3361,7 @@ package body Simul.Execution is
if Res /= Null_Iir then
return Res;
else
- Orig := Sem_Inst.Get_Origin (Spec);
+ Orig := Vhdl.Sem_Inst.Get_Origin (Spec);
return Get_Protected_Type_Body_Origin (Orig);
end if;
end Get_Protected_Type_Body_Origin;
diff --git a/src/vhdl/std_package.adb b/src/vhdl/std_package.adb
index a04fafd4c..5dd659d6a 100644
--- a/src/vhdl/std_package.adb
+++ b/src/vhdl/std_package.adb
@@ -22,7 +22,7 @@ with Str_Table;
with Std_Names; use Std_Names;
with Flags; use Flags;
with Iirs_Utils;
-with Sem_Utils;
+with Vhdl.Sem_Utils;
with Iir_Chains;
package body Std_Package is
@@ -174,7 +174,7 @@ package body Std_Package is
Set_Expr_Staticness (Res, Locally);
Set_Name_Staticness (Res, Locally);
Set_Enum_Pos (Res, Iir_Int32 (Pos));
- Sem_Utils.Compute_Subprogram_Hash (Res);
+ Vhdl.Sem_Utils.Compute_Subprogram_Hash (Res);
Set_Nth_Element (List, Pos, Res);
return Res;
end Create_Std_Literal;
@@ -195,7 +195,7 @@ package body Std_Package is
is
Nxt : Iir;
begin
- Sem_Utils.Create_Implicit_Operations (Decl, True);
+ Vhdl.Sem_Utils.Create_Implicit_Operations (Decl, True);
-- Update Last_Decl
loop
@@ -359,7 +359,7 @@ package body Std_Package is
Set_Chain (Inter, Inter2);
end if;
- Sem_Utils.Compute_Subprogram_Hash (Decl);
+ Vhdl.Sem_Utils.Compute_Subprogram_Hash (Decl);
Add_Decl (Decl);
end Create_To_String;
@@ -384,7 +384,7 @@ package body Std_Package is
Set_Visible_Flag (Inter, True);
Set_Interface_Declaration_Chain (Decl, Inter);
- Sem_Utils.Compute_Subprogram_Hash (Decl);
+ Vhdl.Sem_Utils.Compute_Subprogram_Hash (Decl);
Add_Decl (Decl);
end Create_Edge_Function;
@@ -980,7 +980,7 @@ package body Std_Package is
Set_Pure_Flag (Function_Now, False);
end if;
Set_Implicit_Definition (Function_Now, Iir_Predefined_Now_Function);
- Sem_Utils.Compute_Subprogram_Hash (Function_Now);
+ Vhdl.Sem_Utils.Compute_Subprogram_Hash (Function_Now);
Add_Decl (Function_Now);
end;
diff --git a/src/vhdl/translate/ortho_front.adb b/src/vhdl/translate/ortho_front.adb
index 208348ef4..3fc6f4e81 100644
--- a/src/vhdl/translate/ortho_front.adb
+++ b/src/vhdl/translate/ortho_front.adb
@@ -29,8 +29,8 @@ with Std_Package;
with Flags;
with Configuration;
with Translation;
-with Sem;
-with Sem_Lib; use Sem_Lib;
+with Vhdl.Sem;
+with Vhdl.Sem_Lib; use Vhdl.Sem_Lib;
with Errorout; use Errorout;
with Errorout.Console;
with GNAT.OS_Lib;
@@ -317,7 +317,7 @@ package body Ortho_Front is
-- Do late analysis checks.
Design := Get_First_Design_Unit (New_Design_File);
while Is_Valid (Design) loop
- Sem.Sem_Analysis_Checks_List
+ Vhdl.Sem.Sem_Analysis_Checks_List
(Design, Is_Warning_Enabled (Warnid_Delayed_Checks));
Design := Get_Chain (Design);
end loop;
diff --git a/src/vhdl/translate/trans-chap12.adb b/src/vhdl/translate/trans-chap12.adb
index 1e39d3456..1659d54fb 100644
--- a/src/vhdl/translate/trans-chap12.adb
+++ b/src/vhdl/translate/trans-chap12.adb
@@ -22,8 +22,8 @@ with Std_Package; use Std_Package;
with Iirs_Utils; use Iirs_Utils;
with Libraries;
with Flags;
-with Sem;
-with Sem_Lib; use Sem_Lib;
+with Vhdl.Sem;
+with Vhdl.Sem_Lib; use Vhdl.Sem_Lib;
with Trans.Chap1;
with Trans.Chap2;
with Trans.Chap6;
@@ -550,7 +550,7 @@ package body Trans.Chap12 is
if Flag_Load_All_Design_Units then
for I in Design_Units.First .. Design_Units.Last loop
Unit := Design_Units.Table (I);
- Sem.Sem_Analysis_Checks_List (Unit, False);
+ Vhdl.Sem.Sem_Analysis_Checks_List (Unit, False);
-- There cannot be remaining checks to do.
pragma Assert
(Get_Analysis_Checks_List (Unit) = Null_Iir_List);
diff --git a/src/vhdl/translate/trans-chap2.adb b/src/vhdl/translate/trans-chap2.adb
index 01703b842..433d18443 100644
--- a/src/vhdl/translate/trans-chap2.adb
+++ b/src/vhdl/translate/trans-chap2.adb
@@ -19,7 +19,7 @@
with Std_Names;
with Std_Package; use Std_Package;
with Errorout; use Errorout;
-with Sem_Inst;
+with Vhdl.Sem_Inst;
with Nodes_Meta;
with Iirs_Utils; use Iirs_Utils;
with Trans.Chap3;
@@ -1377,7 +1377,7 @@ package body Trans.Chap2 is
Kind : constant Iir_Kind := Get_Kind (N);
Fields : constant Fields_Array := Get_Fields (Kind);
F : Fields_Enum;
- Orig : constant Iir := Sem_Inst.Get_Origin (N);
+ Orig : constant Iir := Vhdl.Sem_Inst.Get_Origin (N);
pragma Assert (Orig /= Null_Iir);
Orig_Info : constant Ortho_Info_Acc := Get_Info (Orig);
Info : Ortho_Info_Acc;
@@ -1489,7 +1489,7 @@ package body Trans.Chap2 is
begin
Inter := Chain;
while Inter /= Null_Iir loop
- Orig := Sem_Inst.Get_Origin (Inter);
+ Orig := Vhdl.Sem_Inst.Get_Origin (Inter);
Orig_Info := Get_Info (Orig);
Info := Add_Info (Inter, Orig_Info.Kind);
diff --git a/src/vhdl/translate/translation.adb b/src/vhdl/translate/translation.adb
index 4f66723cf..4c5ba5eca 100644
--- a/src/vhdl/translate/translation.adb
+++ b/src/vhdl/translate/translation.adb
@@ -26,7 +26,7 @@ with Str_Table;
with Files_Map;
with Iirs_Utils; use Iirs_Utils;
with Std_Package; use Std_Package;
-with Sem_Specs;
+with Vhdl.Sem_Specs;
with Libraries;
with Std_Names;
with Vhdl.Canon;
@@ -109,7 +109,7 @@ package body Translation is
is
-- Look for 'FOREIGN.
Attr : constant Iir_Attribute_Value :=
- Sem_Specs.Find_Attribute_Value (Decl, Std_Names.Name_Foreign);
+ Vhdl.Sem_Specs.Find_Attribute_Value (Decl, Std_Names.Name_Foreign);
pragma Assert (Attr /= Null_Iir);
Spec : constant Iir_Attribute_Specification :=
Get_Attribute_Specification (Attr);
diff --git a/src/vhdl/vhdl-canon.adb b/src/vhdl/vhdl-canon.adb
index 2675e7cba..2c27e61d7 100644
--- a/src/vhdl/vhdl-canon.adb
+++ b/src/vhdl/vhdl-canon.adb
@@ -20,9 +20,9 @@ with Iirs_Utils; use Iirs_Utils;
with Types; use Types;
with Flags; use Flags;
with Name_Table;
-with Sem;
-with Sem_Inst;
-with Sem_Specs;
+with Vhdl.Sem;
+with Vhdl.Sem_Inst;
+with Vhdl.Sem_Specs;
with Iir_Chains; use Iir_Chains;
with PSL.Nodes;
with PSL.Rewrites;
diff --git a/src/vhdl/sem.adb b/src/vhdl/vhdl-sem.adb
index c5d9761ac..b1875bc1e 100644
--- a/src/vhdl/sem.adb
+++ b/src/vhdl/vhdl-sem.adb
@@ -20,23 +20,23 @@ with Std_Package; use Std_Package;
with Ieee.Std_Logic_1164;
with Libraries;
with Std_Names;
-with Sem_Scopes; use Sem_Scopes;
-with Sem_Expr; use Sem_Expr;
-with Sem_Names; use Sem_Names;
-with Sem_Specs; use Sem_Specs;
-with Sem_Decls; use Sem_Decls;
-with Sem_Assocs; use Sem_Assocs;
-with Sem_Inst;
-with Sem_Lib; use Sem_Lib;
+with Vhdl.Sem_Scopes; use Vhdl.Sem_Scopes;
+with Vhdl.Sem_Expr; use Vhdl.Sem_Expr;
+with Vhdl.Sem_Names; use Vhdl.Sem_Names;
+with Vhdl.Sem_Specs; use Vhdl.Sem_Specs;
+with Vhdl.Sem_Decls; use Vhdl.Sem_Decls;
+with Vhdl.Sem_Assocs; use Vhdl.Sem_Assocs;
+with Vhdl.Sem_Inst;
+with Vhdl.Sem_Lib; use Vhdl.Sem_Lib;
with Iirs_Utils; use Iirs_Utils;
with Flags; use Flags;
with Str_Table;
-with Sem_Utils;
-with Sem_Stmts; use Sem_Stmts;
+with Vhdl.Sem_Utils;
+with Vhdl.Sem_Stmts; use Vhdl.Sem_Stmts;
with Iir_Chains;
with Xrefs; use Xrefs;
-package body Sem is
+package body Vhdl.Sem is
-- Forward declarations.
procedure Sem_Context_Clauses (Unit: Iir);
procedure Sem_Block_Configuration
@@ -3311,4 +3311,4 @@ package body Sem is
Current_Design_Unit := Old_Design_Unit;
Pop_Signals_Declarative_Part (Implicit);
end Semantic;
-end Sem;
+end Vhdl.Sem;
diff --git a/src/vhdl/sem.ads b/src/vhdl/vhdl-sem.ads
index c42301031..c6bb46bd8 100644
--- a/src/vhdl/sem.ads
+++ b/src/vhdl/vhdl-sem.ads
@@ -18,7 +18,7 @@
with Iirs; use Iirs;
with Types; use Types;
-package Sem is
+package Vhdl.Sem is
-- Semantic analysis for chapters 1, 2, 10 (uses clauses) and 11.
-- Do the semantic analysis of design unit DESIGN_UNIT.
@@ -91,4 +91,4 @@ package Sem is
-- uninstantiated package.
function Sem_Uninstantiated_Package_Name (Decl : Iir) return Iir;
-end Sem;
+end Vhdl.Sem;
diff --git a/src/vhdl/sem_assocs.adb b/src/vhdl/vhdl-sem_assocs.adb
index b04962c58..146b582bc 100644
--- a/src/vhdl/sem_assocs.adb
+++ b/src/vhdl/vhdl-sem_assocs.adb
@@ -22,15 +22,15 @@ with Types; use Types;
with Iirs_Utils; use Iirs_Utils;
with Vhdl.Parse;
with Std_Names;
-with Sem_Names; use Sem_Names;
-with Sem_Types;
-with Sem_Decls;
+with Vhdl.Sem_Names; use Vhdl.Sem_Names;
+with Vhdl.Sem_Types;
+with Vhdl.Sem_Decls;
with Std_Package;
-with Sem_Scopes;
+with Vhdl.Sem_Scopes;
with Iir_Chains; use Iir_Chains;
with Xrefs;
-package body Sem_Assocs is
+package body Vhdl.Sem_Assocs is
function Rewrite_Non_Object_Association (Assoc : Iir; Inter : Iir)
return Iir
is
@@ -2568,4 +2568,4 @@ package body Sem_Assocs is
Pos := Pos + 1;
end loop;
end Sem_Association_Chain;
-end Sem_Assocs;
+end Vhdl.Sem_Assocs;
diff --git a/src/vhdl/sem_assocs.ads b/src/vhdl/vhdl-sem_assocs.ads
index 9563138ce..632956c3d 100644
--- a/src/vhdl/sem_assocs.ads
+++ b/src/vhdl/vhdl-sem_assocs.ads
@@ -16,9 +16,9 @@
-- Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-- 02111-1307, USA.
with Iirs; use Iirs;
-with Sem_Expr; use Sem_Expr;
+with Vhdl.Sem_Expr; use Vhdl.Sem_Expr;
-package Sem_Assocs is
+package Vhdl.Sem_Assocs is
-- Rewrite the association chain by changing the kind of assocation
-- corresponding to non-object interfaces. Such an association mustn't be
-- handled an like association for object as the actual is not an
@@ -65,4 +65,4 @@ package Sem_Assocs is
procedure Check_Port_Association_Bounds_Restrictions
(Formal : Iir; Actual : Iir; Assoc : Iir);
-end Sem_Assocs;
+end Vhdl.Sem_Assocs;
diff --git a/src/vhdl/sem_decls.adb b/src/vhdl/vhdl-sem_decls.adb
index 6e1a745c0..f8e380c95 100644
--- a/src/vhdl/sem_decls.adb
+++ b/src/vhdl/vhdl-sem_decls.adb
@@ -23,18 +23,18 @@ with Flags; use Flags;
with Std_Package; use Std_Package;
with Evaluation; use Evaluation;
with Iirs_Utils; use Iirs_Utils;
-with Sem; use Sem;
-with Sem_Utils; use Sem_Utils;
-with Sem_Expr; use Sem_Expr;
-with Sem_Scopes; use Sem_Scopes;
-with Sem_Names; use Sem_Names;
-with Sem_Specs; use Sem_Specs;
-with Sem_Types; use Sem_Types;
-with Sem_Psl;
-with Sem_Inst;
+with Vhdl.Sem; use Vhdl.Sem;
+with Vhdl.Sem_Utils; use Vhdl.Sem_Utils;
+with Vhdl.Sem_Expr; use Vhdl.Sem_Expr;
+with Vhdl.Sem_Scopes; use Vhdl.Sem_Scopes;
+with Vhdl.Sem_Names; use Vhdl.Sem_Names;
+with Vhdl.Sem_Specs; use Vhdl.Sem_Specs;
+with Vhdl.Sem_Types; use Vhdl.Sem_Types;
+with Vhdl.Sem_Psl;
+with Vhdl.Sem_Inst;
with Xrefs; use Xrefs;
-package body Sem_Decls is
+package body Vhdl.Sem_Decls is
-- Region that can declare signals. Used to add implicit declarations.
Current_Signals_Region : Implicit_Signal_Declaration_Type :=
(Null_Iir, Null_Iir, Null_Iir, False, Null_Iir);
@@ -2339,4 +2339,4 @@ package body Sem_Decls is
Set_Expr_Staticness (Iterator, Staticness);
end Sem_Iterator;
-end Sem_Decls;
+end Vhdl.Sem_Decls;
diff --git a/src/vhdl/sem_decls.ads b/src/vhdl/vhdl-sem_decls.ads
index 4362a34fd..99609b5e3 100644
--- a/src/vhdl/sem_decls.ads
+++ b/src/vhdl/vhdl-sem_decls.ads
@@ -17,7 +17,7 @@
-- 02111-1307, USA.
with Iirs; use Iirs;
-package Sem_Decls is
+package Vhdl.Sem_Decls is
-- Analyze an interface chain.
procedure Sem_Interface_Chain (Interface_Chain: Iir;
Interface_Kind : Interface_Kind_Type);
@@ -102,4 +102,4 @@ private
-- will be appended to LAST_DECL.
Last_Decl : Iir;
end record;
-end Sem_Decls;
+end Vhdl.Sem_Decls;
diff --git a/src/vhdl/sem_expr.adb b/src/vhdl/vhdl-sem_expr.adb
index e26739bde..9ac79c601 100644
--- a/src/vhdl/sem_expr.adb
+++ b/src/vhdl/vhdl-sem_expr.adb
@@ -20,21 +20,21 @@ with Grt.Algos;
with Std_Package; use Std_Package;
with Errorout; use Errorout;
with Flags; use Flags;
-with Sem_Scopes; use Sem_Scopes;
-with Sem_Names; use Sem_Names;
-with Sem;
+with Vhdl.Sem_Scopes; use Vhdl.Sem_Scopes;
+with Vhdl.Sem_Names; use Vhdl.Sem_Names;
+with Vhdl.Sem;
with Name_Table;
with Str_Table;
with Iirs_Utils; use Iirs_Utils;
with Evaluation; use Evaluation;
with Iir_Chains; use Iir_Chains;
-with Sem_Types;
-with Sem_Stmts; use Sem_Stmts;
-with Sem_Assocs; use Sem_Assocs;
-with Sem_Decls;
+with Vhdl.Sem_Types;
+with Vhdl.Sem_Stmts; use Vhdl.Sem_Stmts;
+with Vhdl.Sem_Assocs; use Vhdl.Sem_Assocs;
+with Vhdl.Sem_Decls;
with Xrefs; use Xrefs;
-package body Sem_Expr is
+package body Vhdl.Sem_Expr is
-- Replace type of TARGET by A_TYPE.
-- If TARGET has already a type, it must be an overload list, and in this
@@ -5226,4 +5226,4 @@ package body Sem_Expr is
end if;
end Sem_Condition;
-end Sem_Expr;
+end Vhdl.Sem_Expr;
diff --git a/src/vhdl/sem_expr.ads b/src/vhdl/vhdl-sem_expr.ads
index 1e6ada5ba..4e96aa5be 100644
--- a/src/vhdl/sem_expr.ads
+++ b/src/vhdl/vhdl-sem_expr.ads
@@ -20,7 +20,7 @@ with Ada.Unchecked_Deallocation;
with Types; use Types;
with Iirs; use Iirs;
-package Sem_Expr is
+package Vhdl.Sem_Expr is
-- Set semantic to EXPR.
-- Replace simple_name with the referenced node,
-- Set type to nodes,
@@ -267,4 +267,4 @@ package Sem_Expr is
-- To be used after Sem_Expression_Wildcard to update list ATYPE of
-- possible types.
procedure Merge_Wildcard_Type (Expr : Iir; Atype : in out Iir);
-end Sem_Expr;
+end Vhdl.Sem_Expr;
diff --git a/src/vhdl/sem_inst.adb b/src/vhdl/vhdl-sem_inst.adb
index 54f37a2f6..8d73a7a2d 100644
--- a/src/vhdl/sem_inst.adb
+++ b/src/vhdl/vhdl-sem_inst.adb
@@ -21,9 +21,9 @@ with Types; use Types;
with Files_Map;
with Iirs_Utils; use Iirs_Utils;
with Errorout; use Errorout;
-with Sem_Utils;
+with Vhdl.Sem_Utils;
-package body Sem_Inst is
+package body Vhdl.Sem_Inst is
-- Table of origin. This is an extension of vhdl nodes to track the
-- origin of a node. If a node has a non-null origin, then the node was
-- instantiated for the origin node.
@@ -1214,4 +1214,4 @@ package body Sem_Inst is
end loop;
end Substitute_On_Chain;
-end Sem_Inst;
+end Vhdl.Sem_Inst;
diff --git a/src/vhdl/sem_inst.ads b/src/vhdl/vhdl-sem_inst.ads
index 804451272..48d72b770 100644
--- a/src/vhdl/sem_inst.ads
+++ b/src/vhdl/vhdl-sem_inst.ads
@@ -16,7 +16,7 @@
with Iirs; use Iirs;
-package Sem_Inst is
+package Vhdl.Sem_Inst is
-- Return the origin of node N, the node from which N was instantiated.
-- If N is not an instance, this function returns Null_Iir.
function Get_Origin (N : Iir) return Iir;
@@ -33,4 +33,4 @@ package Sem_Inst is
-- Deep copy of ORIG. Doesn't change location.
function Copy_Tree (Orig : Iir) return Iir;
-end Sem_Inst;
+end Vhdl.Sem_Inst;
diff --git a/src/vhdl/sem_lib.adb b/src/vhdl/vhdl-sem_lib.adb
index 7affaaadc..4b2319c09 100644
--- a/src/vhdl/sem_lib.adb
+++ b/src/vhdl/vhdl-sem_lib.adb
@@ -25,12 +25,12 @@ with Vhdl.Scanner;
with Vhdl.Parse;
with Vhdl.Disp_Tree;
with Vhdl.Disp_Vhdl;
-with Sem;
+with Vhdl.Sem;
with Post_Sems;
with Vhdl.Canon;
with Nodes_GC;
-package body Sem_Lib is
+package body Vhdl.Sem_Lib is
procedure Error_Lib_Msg (Msg : String; Arg1 : Earg_Type) is
begin
Report_Msg (Msgid_Error, Library, No_Location, Msg, (1 => Arg1));
@@ -408,4 +408,4 @@ package body Sem_Lib is
end if;
return Design_Unit;
end Load_Secondary_Unit;
-end Sem_Lib;
+end Vhdl.Sem_Lib;
diff --git a/src/vhdl/sem_lib.ads b/src/vhdl/vhdl-sem_lib.ads
index 7f57833b5..812279b90 100644
--- a/src/vhdl/sem_lib.ads
+++ b/src/vhdl/vhdl-sem_lib.ads
@@ -18,7 +18,7 @@
with Types; use Types;
with Iirs; use Iirs;
-package Sem_Lib is
+package Vhdl.Sem_Lib is
-- Start the analyse a file (ie load and parse it).
-- The file is read from the current directory (unless FILE_NAME is an
-- absolute path).
@@ -55,4 +55,4 @@ package Sem_Lib is
-- Analyze UNIT.
procedure Finish_Compilation
(Unit : Iir_Design_Unit; Main : Boolean := False);
-end Sem_Lib;
+end Vhdl.Sem_Lib;
diff --git a/src/vhdl/sem_names.adb b/src/vhdl/vhdl-sem_names.adb
index 38d372c53..d72af8c28 100644
--- a/src/vhdl/sem_names.adb
+++ b/src/vhdl/vhdl-sem_names.adb
@@ -24,19 +24,19 @@ with Std_Package; use Std_Package;
with Types; use Types;
with Iir_Chains; use Iir_Chains;
with Std_Names;
-with Sem;
-with Sem_Lib; use Sem_Lib;
-with Sem_Scopes; use Sem_Scopes;
-with Sem_Expr; use Sem_Expr;
-with Sem_Stmts; use Sem_Stmts;
-with Sem_Decls; use Sem_Decls;
-with Sem_Assocs; use Sem_Assocs;
-with Sem_Specs;
-with Sem_Types;
-with Sem_Psl;
+with Vhdl.Sem;
+with Vhdl.Sem_Lib; use Vhdl.Sem_Lib;
+with Vhdl.Sem_Scopes; use Vhdl.Sem_Scopes;
+with Vhdl.Sem_Expr; use Vhdl.Sem_Expr;
+with Vhdl.Sem_Stmts; use Vhdl.Sem_Stmts;
+with Vhdl.Sem_Decls; use Vhdl.Sem_Decls;
+with Vhdl.Sem_Assocs; use Vhdl.Sem_Assocs;
+with Vhdl.Sem_Specs;
+with Vhdl.Sem_Types;
+with Vhdl.Sem_Psl;
with Xrefs; use Xrefs;
-package body Sem_Names is
+package body Vhdl.Sem_Names is
-- Finish the analyze of NAME using RES as named entity.
-- This is called when the analyze is finished and an uniq
-- interpretation has been determined (RES).
@@ -4310,4 +4310,4 @@ package body Sem_Names is
+Get_Named_Entity (Name));
end if;
end Error_Class_Match;
-end Sem_Names;
+end Vhdl.Sem_Names;
diff --git a/src/vhdl/sem_names.ads b/src/vhdl/vhdl-sem_names.ads
index 542ed4d07..d5ed1a462 100644
--- a/src/vhdl/sem_names.ads
+++ b/src/vhdl/vhdl-sem_names.ads
@@ -17,7 +17,7 @@
-- 02111-1307, USA.
with Iirs; use Iirs;
-package Sem_Names is
+package Vhdl.Sem_Names is
-- In VHDL, most of name notations are ambiguous:
-- P.N is either
-- an expanded name or
@@ -156,4 +156,4 @@ package Sem_Names is
-- Emit an error for NAME that doesn't match its class CLASS_NAME.
procedure Error_Class_Match (Name : Iir; Class_Name : String);
-end Sem_Names;
+end Vhdl.Sem_Names;
diff --git a/src/vhdl/sem_psl.adb b/src/vhdl/vhdl-sem_psl.adb
index 346802944..41a2e74d9 100644
--- a/src/vhdl/sem_psl.adb
+++ b/src/vhdl/vhdl-sem_psl.adb
@@ -21,10 +21,10 @@ with PSL.Nodes; use PSL.Nodes;
with PSL.Subsets;
with PSL.Hash;
-with Sem_Expr;
-with Sem_Stmts; use Sem_Stmts;
-with Sem_Scopes;
-with Sem_Names;
+with Vhdl.Sem_Expr;
+with Vhdl.Sem_Stmts; use Vhdl.Sem_Stmts;
+with Vhdl.Sem_Scopes;
+with Vhdl.Sem_Names;
with Std_Names;
with Iirs_Utils; use Iirs_Utils;
with Evaluation; use Evaluation;
@@ -33,7 +33,7 @@ with Ieee.Std_Logic_1164;
with Errorout; use Errorout;
with Xrefs; use Xrefs;
-package body Sem_Psl is
+package body Vhdl.Sem_Psl is
procedure Sem_Psl_Directive_Clock (Stmt : Iir; Prop : in out Node);
-- Return TRUE iff Atype is a PSL boolean type.
@@ -805,4 +805,4 @@ package body Sem_Psl is
return Null_Iir;
end Sem_Psl_Name;
-end Sem_Psl;
+end Vhdl.Sem_Psl;
diff --git a/src/vhdl/sem_psl.ads b/src/vhdl/vhdl-sem_psl.ads
index 6d2bf75ea..396927f4d 100644
--- a/src/vhdl/sem_psl.ads
+++ b/src/vhdl/vhdl-sem_psl.ads
@@ -18,7 +18,7 @@
with Iirs; use Iirs;
-package Sem_Psl is
+package Vhdl.Sem_Psl is
procedure Sem_Psl_Declaration (Stmt : Iir);
procedure Sem_Psl_Endpoint_Declaration (Stmt : Iir);
@@ -28,4 +28,4 @@ package Sem_Psl is
procedure Sem_Psl_Cover_Statement (Stmt : Iir);
procedure Sem_Psl_Default_Clock (Stmt : Iir);
function Sem_Psl_Name (Name : Iir) return Iir;
-end Sem_Psl;
+end Vhdl.Sem_Psl;
diff --git a/src/vhdl/sem_scopes.adb b/src/vhdl/vhdl-sem_scopes.adb
index e4f780961..8e616bd4b 100644
--- a/src/vhdl/sem_scopes.adb
+++ b/src/vhdl/vhdl-sem_scopes.adb
@@ -23,7 +23,7 @@ with Files_Map; use Files_Map;
with Errorout; use Errorout;
with Iirs_Utils; use Iirs_Utils;
-package body Sem_Scopes is
+package body Vhdl.Sem_Scopes is
-- An interpretation cell is the element of the simply linked list
-- of interpretation for an identifier.
-- Interpretation cells are stored in table Interpretations.
@@ -1669,4 +1669,4 @@ package body Sem_Scopes is
end;
end loop;
end Disp_Scopes;
-end Sem_Scopes;
+end Vhdl.Sem_Scopes;
diff --git a/src/vhdl/sem_scopes.ads b/src/vhdl/vhdl-sem_scopes.ads
index 3503d4fb6..93aad18cd 100644
--- a/src/vhdl/sem_scopes.ads
+++ b/src/vhdl/vhdl-sem_scopes.ads
@@ -18,7 +18,7 @@
with Iirs; use Iirs;
with Types; use Types;
-package Sem_Scopes is
+package Vhdl.Sem_Scopes is
-- The purpose of SEM_NAME package is to handle association between
-- identifiers and declarations.
@@ -217,4 +217,4 @@ private
No_Name_Interpretation : constant Name_Interpretation_Type := 0;
First_Valid_Interpretation : constant Name_Interpretation_Type := 1;
-end Sem_Scopes;
+end Vhdl.Sem_Scopes;
diff --git a/src/vhdl/sem_specs.adb b/src/vhdl/vhdl-sem_specs.adb
index 429431539..bd21e7e47 100644
--- a/src/vhdl/sem_specs.adb
+++ b/src/vhdl/vhdl-sem_specs.adb
@@ -16,24 +16,24 @@
-- Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-- 02111-1307, USA.
with Iirs_Utils; use Iirs_Utils;
-with Sem_Expr; use Sem_Expr;
-with Sem_Names; use Sem_Names;
+with Vhdl.Sem_Expr; use Vhdl.Sem_Expr;
+with Vhdl.Sem_Names; use Vhdl.Sem_Names;
with Evaluation; use Evaluation;
with Std_Package; use Std_Package;
with Errorout; use Errorout;
-with Sem; use Sem;
-with Sem_Lib; use Sem_Lib;
-with Sem_Scopes; use Sem_Scopes;
-with Sem_Assocs; use Sem_Assocs;
+with Vhdl.Sem; use Vhdl.Sem;
+with Vhdl.Sem_Lib; use Vhdl.Sem_Lib;
+with Vhdl.Sem_Scopes; use Vhdl.Sem_Scopes;
+with Vhdl.Sem_Assocs; use Vhdl.Sem_Assocs;
with Libraries;
with Iir_Chains; use Iir_Chains;
with Flags; use Flags;
with Std_Names;
-with Sem_Decls;
+with Vhdl.Sem_Decls;
with Xrefs; use Xrefs;
with Back_End;
-package body Sem_Specs is
+package body Vhdl.Sem_Specs is
function Get_Entity_Class_Kind (Decl : Iir) return Vhdl.Tokens.Token_Type
is
use Vhdl.Tokens;
@@ -1925,4 +1925,4 @@ package body Sem_Specs is
Decl := Get_Chain (Decl);
end loop;
end Sem_Specification_Chain;
-end Sem_Specs;
+end Vhdl.Sem_Specs;
diff --git a/src/vhdl/sem_specs.ads b/src/vhdl/vhdl-sem_specs.ads
index 170df72fb..5c4fef962 100644
--- a/src/vhdl/sem_specs.ads
+++ b/src/vhdl/vhdl-sem_specs.ads
@@ -19,7 +19,7 @@ with Types; use Types;
with Iirs; use Iirs;
with Vhdl.Tokens;
-package Sem_Specs is
+package Vhdl.Sem_Specs is
-- Return the attribute_value for named entity ENT and attribute identifier
-- ID. Return Null_Iir if ENT was not decorated with attribute ID.
function Find_Attribute_Value (Ent : Iir; Id : Name_Id) return Iir;
@@ -96,4 +96,4 @@ package Sem_Specs is
return Iir_Design_Unit;
procedure Sem_Specification_Chain (Decls_Parent : Iir; Parent_Stmts: Iir);
-end Sem_Specs;
+end Vhdl.Sem_Specs;
diff --git a/src/vhdl/sem_stmts.adb b/src/vhdl/vhdl-sem_stmts.adb
index 30c0de209..9a616896a 100644
--- a/src/vhdl/sem_stmts.adb
+++ b/src/vhdl/vhdl-sem_stmts.adb
@@ -18,21 +18,21 @@
with Errorout; use Errorout;
with Types; use Types;
with Flags; use Flags;
-with Sem_Specs; use Sem_Specs;
+with Vhdl.Sem_Specs; use Vhdl.Sem_Specs;
with Std_Package; use Std_Package;
-with Sem; use Sem;
-with Sem_Decls; use Sem_Decls;
-with Sem_Expr; use Sem_Expr;
-with Sem_Names; use Sem_Names;
-with Sem_Scopes; use Sem_Scopes;
-with Sem_Types;
-with Sem_Psl;
+with Vhdl.Sem; use Vhdl.Sem;
+with Vhdl.Sem_Decls; use Vhdl.Sem_Decls;
+with Vhdl.Sem_Expr; use Vhdl.Sem_Expr;
+with Vhdl.Sem_Names; use Vhdl.Sem_Names;
+with Vhdl.Sem_Scopes; use Vhdl.Sem_Scopes;
+with Vhdl.Sem_Types;
+with Vhdl.Sem_Psl;
with Std_Names;
with Evaluation; use Evaluation;
with Iirs_Utils; use Iirs_Utils;
with Xrefs; use Xrefs;
-package body Sem_Stmts is
+package body Vhdl.Sem_Stmts is
-- Process is the scope, this is also the process for which drivers can
-- be created.
-- Note: FIRST_STMT is the first statement, which can be get by:
@@ -2180,4 +2180,4 @@ package body Sem_Stmts is
end if;
end if;
end Sem_Add_Driver;
-end Sem_Stmts;
+end Vhdl.Sem_Stmts;
diff --git a/src/vhdl/sem_stmts.ads b/src/vhdl/vhdl-sem_stmts.ads
index 5df75e09c..81c7806aa 100644
--- a/src/vhdl/sem_stmts.ads
+++ b/src/vhdl/vhdl-sem_stmts.ads
@@ -17,7 +17,7 @@
-- 02111-1307, USA.
with Iirs; use Iirs;
-package Sem_Stmts is
+package Vhdl.Sem_Stmts is
-- Analyze declarations and concurrent statements of BLK, which is
-- either an architecture_declaration, and entity_declaration,
-- a block_statement or a generate_statement_body.
@@ -55,4 +55,4 @@ package Sem_Stmts is
-- The current statement list does not belong to a process,
-- SIG is a formal signal interface.
procedure Sem_Add_Driver (Sig : Iir; Stmt : Iir);
-end Sem_Stmts;
+end Vhdl.Sem_Stmts;
diff --git a/src/vhdl/sem_types.adb b/src/vhdl/vhdl-sem_types.adb
index 4bb4ac2dd..20651c000 100644
--- a/src/vhdl/sem_types.adb
+++ b/src/vhdl/vhdl-sem_types.adb
@@ -20,12 +20,12 @@ with Flags; use Flags;
with Types; use Types;
with Errorout; use Errorout;
with Evaluation; use Evaluation;
-with Sem_Utils;
-with Sem_Expr; use Sem_Expr;
-with Sem_Scopes; use Sem_Scopes;
-with Sem_Names; use Sem_Names;
-with Sem_Decls;
-with Sem_Inst;
+with Vhdl.Sem_Utils;
+with Vhdl.Sem_Expr; use Vhdl.Sem_Expr;
+with Vhdl.Sem_Scopes; use Vhdl.Sem_Scopes;
+with Vhdl.Sem_Names; use Vhdl.Sem_Names;
+with Vhdl.Sem_Decls;
+with Vhdl.Sem_Inst;
with Name_Table;
with Std_Names;
with Iirs_Utils; use Iirs_Utils;
@@ -33,7 +33,7 @@ with Std_Package; use Std_Package;
with Ieee.Std_Logic_1164;
with Xrefs; use Xrefs;
-package body Sem_Types is
+package body Vhdl.Sem_Types is
-- Mark the resolution function (this may be required by the back-end to
-- generate resolver).
procedure Mark_Resolution_Function (Subtyp : Iir)
@@ -2379,4 +2379,4 @@ package body Sem_Types is
end case;
end Sem_Subnature_Indication;
-end Sem_Types;
+end Vhdl.Sem_Types;
diff --git a/src/vhdl/sem_types.ads b/src/vhdl/vhdl-sem_types.ads
index f4ad3ff74..33648b870 100644
--- a/src/vhdl/sem_types.ads
+++ b/src/vhdl/vhdl-sem_types.ads
@@ -17,7 +17,7 @@
-- 02111-1307, USA.
with Iirs; use Iirs;
-package Sem_Types is
+package Vhdl.Sem_Types is
-- Analyze of types (LRM93 3 / LRM08 5)
-- Analyze subtype indication DEF.
@@ -65,4 +65,4 @@ package Sem_Types is
-- Although a nature is not a type, it is patterned like a type.
function Sem_Subnature_Indication (Def: Iir) return Iir;
-end Sem_Types;
+end Vhdl.Sem_Types;
diff --git a/src/vhdl/sem_utils.adb b/src/vhdl/vhdl-sem_utils.adb
index f1d57d85f..06dfa5a50 100644
--- a/src/vhdl/sem_utils.adb
+++ b/src/vhdl/vhdl-sem_utils.adb
@@ -25,7 +25,7 @@ with Ieee.Std_Logic_1164;
with Std_Names;
with Std_Package; use Std_Package;
-package body Sem_Utils is
+package body Vhdl.Sem_Utils is
procedure Compute_Subprogram_Hash (Subprg : Iir)
is
type Hash_Type is mod 2**32;
@@ -1036,4 +1036,4 @@ package body Sem_Utils is
end;
end if;
end Create_Implicit_Operations;
-end Sem_Utils;
+end Vhdl.Sem_Utils;
diff --git a/src/vhdl/sem_utils.ads b/src/vhdl/vhdl-sem_utils.ads
index 263a9de31..b7fc8082e 100644
--- a/src/vhdl/sem_utils.ads
+++ b/src/vhdl/vhdl-sem_utils.ads
@@ -17,7 +17,7 @@
-- 02111-1307, USA.
with Iirs; use Iirs;
-package Sem_Utils is
+package Vhdl.Sem_Utils is
-- Compute and set the hash profile of a subprogram or enumeration clause.
procedure Compute_Subprogram_Hash (Subprg : Iir);
@@ -27,4 +27,4 @@ package Sem_Utils is
-- Create predefined operations for DECL.
procedure Create_Implicit_Operations
(Decl : Iir; Is_Std_Standard : Boolean := False);
-end Sem_Utils;
+end Vhdl.Sem_Utils;