diff options
-rw-r--r-- | testsuite/gna/issue1823/entity2.vhdl | 11 | ||||
-rw-r--r-- | testsuite/gna/issue1823/entity3.vhdl | 11 | ||||
-rw-r--r-- | testsuite/gna/issue1823/entity4.vhdl | 11 | ||||
-rw-r--r-- | testsuite/gna/issue1823/entity_1.vhdl | 37 | ||||
-rwxr-xr-x | testsuite/gna/issue1823/testsuite.sh | 14 |
5 files changed, 84 insertions, 0 deletions
diff --git a/testsuite/gna/issue1823/entity2.vhdl b/testsuite/gna/issue1823/entity2.vhdl new file mode 100644 index 000000000..2d9b592ec --- /dev/null +++ b/testsuite/gna/issue1823/entity2.vhdl @@ -0,0 +1,11 @@ +entity entity2 is +end; + +architecture behav of entity2 is + signal Clock : bit; +begin + inst2: counter2(a to b) + port map ( + clk => Clock + ); +end architecture behav; diff --git a/testsuite/gna/issue1823/entity3.vhdl b/testsuite/gna/issue1823/entity3.vhdl new file mode 100644 index 000000000..0e502cb96 --- /dev/null +++ b/testsuite/gna/issue1823/entity3.vhdl @@ -0,0 +1,11 @@ +entity entity3 is +end; + +architecture behav of entity3 is + signal Clock : bit; +begin + inst2: counter2.all + port map ( + clk => Clock + ); +end architecture behav; diff --git a/testsuite/gna/issue1823/entity4.vhdl b/testsuite/gna/issue1823/entity4.vhdl new file mode 100644 index 000000000..3629d3d17 --- /dev/null +++ b/testsuite/gna/issue1823/entity4.vhdl @@ -0,0 +1,11 @@ +entity entity3 is +end; + +architecture behav of entity3 is + signal Clock : bit; +begin + inst2: (a, b) + port map ( + clk => Clock + ); +end architecture behav; diff --git a/testsuite/gna/issue1823/entity_1.vhdl b/testsuite/gna/issue1823/entity_1.vhdl new file mode 100644 index 000000000..137216d3a --- /dev/null +++ b/testsuite/gna/issue1823/entity_1.vhdl @@ -0,0 +1,37 @@ +entity entity_1 is +end entity entity_1; + +architecture behav of entity_1 is + signal Clock : bit; +begin + inst1: entity work.counter1(rtl) + generic map ( + BITS => 8 + ) + port map ( + clk => Clock + ); + + inst2: counter2(rtl) + port map ( + clk => Clock + ); + + inst3: component counter3 + port map ( + clk => Clock + ); + + inst4: configuration counter4 + port map ( + clk => Clock + ); + + blk: block + begin + inst5: entity work.counter1(rtl) + port map ( + clk => Clock + ); + end block; +end architecture behav; diff --git a/testsuite/gna/issue1823/testsuite.sh b/testsuite/gna/issue1823/testsuite.sh new file mode 100755 index 000000000..b49d6bd7f --- /dev/null +++ b/testsuite/gna/issue1823/testsuite.sh @@ -0,0 +1,14 @@ +#! /bin/sh + +. ../../testenv.sh + +for f in entity_1.vhdl entity2.vhdl entity3.vhdl; do + echo "parsing $f" + if $GHDL -i $f; then + echo "error expected during parse" + fi +done + +clean + +echo "Test successful" |