3 files changed, 59 insertions, 0 deletions
diff --git a/testsuite/synth/issue1007/test_entity.vhdl b/testsuite/synth/issue1007/test_entity.vhdl
new file mode 100644
index 000000000..3f70d8948
--- /dev/null
+++ b/testsuite/synth/issue1007/test_entity.vhdl
@@ -0,0 +1,22 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity test_entity is
+    generic(
+        DO_GEN : boolean := false
+        );
+    port(
+        val_out : out std_logic
+        );
+end test_entity;
+
+architecture rtl of test_entity is
+begin
+    set_val_1: if DO_GEN generate
+        val_out <= '1';
+    end generate;
+
+    set_val_0: if not DO_GEN generate
+        val_out <= '0';
+    end generate;
+end;
diff --git a/testsuite/synth/issue1007/test_wrapper.vhdl b/testsuite/synth/issue1007/test_wrapper.vhdl
new file mode 100644
index 000000000..5fced5cb8
--- /dev/null
+++ b/testsuite/synth/issue1007/test_wrapper.vhdl
@@ -0,0 +1,28 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity test_wrapper is
+    port(
+        val1_out : out std_logic;
+        val2_out : out std_logic
+        );
+end test_wrapper;
+
+architecture rtl of test_wrapper is
+begin
+    entity_0 : entity work.test_entity
+        generic map (
+            DO_GEN => true
+            )
+        port map (
+            val_out => val1_out
+            );
+
+    entity_1 : entity work.test_entity
+        generic map (
+            DO_GEN => false
+            )
+        port map (
+            val_out => val2_out
+            );
+end;
diff --git a/testsuite/synth/issue1007/testsuite.sh b/testsuite/synth/issue1007/testsuite.sh
new file mode 100755
index 000000000..3dc84526d
--- /dev/null
+++ b/testsuite/synth/issue1007/testsuite.sh
@@ -0,0 +1,9 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+synth test_entity.vhdl test_wrapper.vhdl -e > syn_test_wrapper.vhdl
+analyze syn_test_wrapper.vhdl
+clean
+
+echo "Test successful"