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-rw-r--r--testsuite/gna/issue1875/test.vhdl19
-rwxr-xr-xtestsuite/gna/issue1875/testsuite.sh11
2 files changed, 30 insertions, 0 deletions
diff --git a/testsuite/gna/issue1875/test.vhdl b/testsuite/gna/issue1875/test.vhdl
new file mode 100644
index 000000000..e1540e551
--- /dev/null
+++ b/testsuite/gna/issue1875/test.vhdl
@@ -0,0 +1,19 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.VITAL_timing.all;
+use IEEE.VITAL_primitives.all;
+
+entity test is
+ port (
+ CLK : in std_logic_vector(1 downto 0)
+ );
+ attribute VITAL_LEVEL0 of test : entity is TRUE;
+end test;
+
+architecture VITAL_ACT of test is
+begin
+ process
+ begin
+ wait;
+ end process;
+end architecture;
diff --git a/testsuite/gna/issue1875/testsuite.sh b/testsuite/gna/issue1875/testsuite.sh
new file mode 100755
index 000000000..a3abac41b
--- /dev/null
+++ b/testsuite/gna/issue1875/testsuite.sh
@@ -0,0 +1,11 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+export GHDL_STD_FLAGS="--std=08 -frelaxed"
+analyze test.vhdl
+elab_simulate test
+
+clean
+
+echo "Test successful"