testsuite/pyunit/libghdl: add more tests for comments gathering

15 files changed, 204 insertions, 16 deletions

diff --git a/testsuite/pyunit/libghdl/Comments.py b/testsuite/pyunit/libghdl/Comments.py
index 9a4daf007..82da89693 100644
--- a/testsuite/pyunit/libghdl/Comments.py
+++ b/testsuite/pyunit/libghdl/Comments.py
@@ -4,7 +4,7 @@ from unittest import TestCase, skip, expectedFailure
 import pyGHDL.libghdl as libghdl
 from pyGHDL.libghdl import name_table, files_map, errorout_console, flags
 from pyGHDL.libghdl import file_comments
-from pyGHDL.libghdl.vhdl import nodes, sem_lib
+from pyGHDL.libghdl.vhdl import nodes, flists, sem_lib
 
 
 if __name__ == "__main__":
@@ -44,11 +44,32 @@ class Instantiate(TestCase):
                             "no :{}: in '{}'".format(name, s))
             idx = file_comments.Get_Next_Comment(f, idx)
 
-    def checkInterfaces(self, first) -> None:
-        inter = first
-        while inter != nodes.Null_Iir:
-            self.checkComments(inter, self.getIdentifier(inter))
-            inter = nodes.Get_Chain(inter)
+    def checkFlist(self, flist) -> None:
+        for i in range(flists.Length(flist)):
+            e = flists.Get_Nth_Element(flist, i)
+            self.checkComments(e, self.getIdentifier(e))
+
+    def checkDecls(self, first) -> None:
+        decl = first
+        while decl != nodes.Null_Iir:
+            k = nodes.Get_Kind(decl)
+            if (k not in nodes.Iir_Kinds.Specification
+                and k not in nodes.Iir_Kinds.Clause):
+                self.checkComments(decl, self.getIdentifier(decl))
+            if k == nodes.Iir_Kind.Type_Declaration:
+                tdef = nodes.Get_Type_Definition(decl)
+                defk = nodes.Get_Kind(tdef)
+                if defk == nodes.Iir_Kind.Record_Type_Definition:
+                    self.checkFlist(nodes.Get_Elements_Declaration_List(tdef))
+            decl = nodes.Get_Chain(decl)
+
+    def checkConc(self, first) -> None:
+        stmt = first
+        while stmt != nodes.Null_Iir:
+            k = nodes.Get_Kind(stmt)
+            if k in nodes.Iir_Kinds.Process_Statement:
+                self.checkDecls(nodes.Get_Declaration_Chain(stmt))
+            stmt = nodes.Get_Chain(stmt)
 
     def checkFile(self, filename) -> None:
         # Load the file
@@ -63,32 +84,35 @@ class Instantiate(TestCase):
         # Display all design units
         designUnit = nodes.Get_First_Design_Unit(file)
         while designUnit != nodes.Null_Iir:
-            libraryUnit = nodes.Get_Library_Unit(designUnit)
+            unit = nodes.Get_Library_Unit(designUnit)
 
-            k = nodes.Get_Kind(libraryUnit)
-            name = self.getIdentifier(libraryUnit)
+            k = nodes.Get_Kind(unit)
+            name = self.getIdentifier(unit)
 
             if k == nodes.Iir_Kind.Entity_Declaration:
                 self.checkComments(designUnit, name)
-                self.checkComments(libraryUnit, name)
-                self.checkInterfaces(nodes.Get_Generic_Chain(libraryUnit))
-                self.checkInterfaces(nodes.Get_Port_Chain(libraryUnit))
+                self.checkComments(unit, name)
+                self.checkDecls(nodes.Get_Generic_Chain(unit))
+                self.checkDecls(nodes.Get_Port_Chain(unit))
 
             elif k == nodes.Iir_Kind.Architecture_Body:
                 self.checkComments(designUnit, name)
-                self.checkComments(libraryUnit, name)
+                self.checkComments(unit, name)
+                self.checkDecls(nodes.Get_Declaration_Chain(unit))
+                self.checkConc(nodes.Get_Concurrent_Statement_Chain(unit))
 
             elif k == nodes.Iir_Kind.Package_Declaration:
                 self.checkComments(designUnit, name)
-                self.checkComments(libraryUnit, name)
+                self.checkComments(unit, name)
+                self.checkDecls(nodes.Get_Declaration_Chain(unit))
 
             elif k == nodes.Iir_Kind.Context_Declaration:
                 self.checkComments(designUnit, name)
-                self.checkComments(libraryUnit, name)
+                self.checkComments(unit, name)
 
             elif k == nodes.Iir_Kind.Configuration_Declaration:
                 self.checkComments(designUnit, name)
-                self.checkComments(libraryUnit, name)
+                self.checkComments(unit, name)
 
             else:
                 self.fail("Unknown unit.")
@@ -149,3 +173,53 @@ class Instantiate(TestCase):
 
     def test_conf_inside(self) -> None:
         self.checkFile(self._root / "conf_inside.vhdl")
+
+    @expectedFailure
+    def test_const_fail(self) -> None:
+        self.checkFile(self._root / "const_fail.vhdl")
+
+    def test_const(self) -> None:
+        self.checkFile(self._root / "const.vhdl")
+
+    @expectedFailure
+    def test_sig_fail(self) -> None:
+        self.checkFile(self._root / "sig_fail.vhdl")
+
+    def test_sig(self) -> None:
+        self.checkFile(self._root / "sig.vhdl")
+
+    @expectedFailure
+    def test_var_fail(self) -> None:
+        self.checkFile(self._root / "var_fail.vhdl")
+
+    def test_var(self) -> None:
+        self.checkFile(self._root / "var.vhdl")
+
+    @expectedFailure
+    def test_type_fail(self) -> None:
+        self.checkFile(self._root / "type_fail.vhdl")
+
+    def test_type(self) -> None:
+        self.checkFile(self._root / "type.vhdl")
+
+    def test_array(self) -> None:
+        self.checkFile(self._root / "array.vhdl")
+
+    @expectedFailure
+    def test_record_fail(self) -> None:
+        self.checkFile(self._root / "record_fail.vhdl")
+
+    def test_record(self) -> None:
+        self.checkFile(self._root / "record.vhdl")
+
+    @expectedFailure
+    def test_elements_fail(self) -> None:
+        self.checkFile(self._root / "elements_fail.vhdl")
+
+    def test_element_1(self) -> None:
+        self.checkFile(self._root / "element_1.vhdl")
+
+    def test_element_2(self) -> None:
+        self.checkFile(self._root / "element_2.vhdl")
+
+# Empty line before to easy cut & put
diff --git a/testsuite/pyunit/libghdl/array.vhdl b/testsuite/pyunit/libghdl/array.vhdl
new file mode 100644
index 000000000..659f88b4d
--- /dev/null
+++ b/testsuite/pyunit/libghdl/array.vhdl
@@ -0,0 +1,7 @@
+package p is
+
+  constant c : natural := 1;
+
+  --  Comment for :vec:
+  type vec is array(natural) of bit_vector(0 to 1);
+end p;
diff --git a/testsuite/pyunit/libghdl/const.vhdl b/testsuite/pyunit/libghdl/const.vhdl
new file mode 100644
index 000000000..85f347d59
--- /dev/null
+++ b/testsuite/pyunit/libghdl/const.vhdl
@@ -0,0 +1,7 @@
+package p is
+
+  constant c : natural := 1;
+
+  --  Comment for the decl :c1:
+  constant c1 : natural := 3;
+end p;
diff --git a/testsuite/pyunit/libghdl/const_fail.vhdl b/testsuite/pyunit/libghdl/const_fail.vhdl
new file mode 100644
index 000000000..9eaede81b
--- /dev/null
+++ b/testsuite/pyunit/libghdl/const_fail.vhdl
@@ -0,0 +1,7 @@
+package p is
+
+  constant c : natural := 1;
+
+  --  Comment for the decl.
+  constant c1 : natural := 3;
+end p;
diff --git a/testsuite/pyunit/libghdl/element_1.vhdl b/testsuite/pyunit/libghdl/element_1.vhdl
new file mode 100644
index 000000000..f88219bec
--- /dev/null
+++ b/testsuite/pyunit/libghdl/element_1.vhdl
@@ -0,0 +1,7 @@
+package p is
+  type rec is record
+    --  Comment for the first element :a:
+    a : bit;
+    b : bit;
+  end record;
+end p;
diff --git a/testsuite/pyunit/libghdl/element_2.vhdl b/testsuite/pyunit/libghdl/element_2.vhdl
new file mode 100644
index 000000000..324dac9db
--- /dev/null
+++ b/testsuite/pyunit/libghdl/element_2.vhdl
@@ -0,0 +1,7 @@
+package p is
+  type rec is record
+    a : bit;
+    --  Comment for the first element :b:
+    b : bit;
+  end record;
+end p;
diff --git a/testsuite/pyunit/libghdl/elements_fail.vhdl b/testsuite/pyunit/libghdl/elements_fail.vhdl
new file mode 100644
index 000000000..9173524f2
--- /dev/null
+++ b/testsuite/pyunit/libghdl/elements_fail.vhdl
@@ -0,0 +1,7 @@
+package p is
+  type rec is record
+    --  Comment for the first element.
+    a : bit;
+    b : bit;
+  end record;
+end p;
diff --git a/testsuite/pyunit/libghdl/record.vhdl b/testsuite/pyunit/libghdl/record.vhdl
new file mode 100644
index 000000000..9036f0938
--- /dev/null
+++ b/testsuite/pyunit/libghdl/record.vhdl
@@ -0,0 +1,10 @@
+package p is
+
+  constant c : natural := 1;
+
+  --  Comment for :rec:
+  type rec is record
+    a : bit;
+    b : bit;
+  end record;
+end p;
diff --git a/testsuite/pyunit/libghdl/record_fail.vhdl b/testsuite/pyunit/libghdl/record_fail.vhdl
new file mode 100644
index 000000000..fd584f274
--- /dev/null
+++ b/testsuite/pyunit/libghdl/record_fail.vhdl
@@ -0,0 +1,10 @@
+package p is
+
+  constant c : natural := 1;
+
+  --  Comment for the record
+  type rec is record
+    a : bit;
+    b : bit;
+  end record;
+end p;
diff --git a/testsuite/pyunit/libghdl/sig.vhdl b/testsuite/pyunit/libghdl/sig.vhdl
new file mode 100644
index 000000000..785630e7d
--- /dev/null
+++ b/testsuite/pyunit/libghdl/sig.vhdl
@@ -0,0 +1,7 @@
+architecture arch of ent is
+  signal b1 : bit;
+
+  --  Comment for :b2:
+  signal b2 : bit;
+begin
+end arch;
diff --git a/testsuite/pyunit/libghdl/sig_fail.vhdl b/testsuite/pyunit/libghdl/sig_fail.vhdl
new file mode 100644
index 000000000..c686ef2a5
--- /dev/null
+++ b/testsuite/pyunit/libghdl/sig_fail.vhdl
@@ -0,0 +1,7 @@
+architecture arch of ent is
+  signal b1 : bit;
+
+  --  Comment
+  signal b2 : bit;
+begin
+end arch;
diff --git a/testsuite/pyunit/libghdl/type.vhdl b/testsuite/pyunit/libghdl/type.vhdl
new file mode 100644
index 000000000..858c97c08
--- /dev/null
+++ b/testsuite/pyunit/libghdl/type.vhdl
@@ -0,0 +1,7 @@
+package p is
+
+  constant c : natural := 1;
+
+  --  Comment for :vec:
+  type vec is array(natural range <>) of bit_vector(0 to 1);
+end p;
diff --git a/testsuite/pyunit/libghdl/type_fail.vhdl b/testsuite/pyunit/libghdl/type_fail.vhdl
new file mode 100644
index 000000000..a88613a57
--- /dev/null
+++ b/testsuite/pyunit/libghdl/type_fail.vhdl
@@ -0,0 +1,7 @@
+package p is
+
+  constant c : natural := 1;
+
+  --  Comment
+  type vec is array(natural range <>) of bit_vector(0 to 1);
+end p;
diff --git a/testsuite/pyunit/libghdl/var.vhdl b/testsuite/pyunit/libghdl/var.vhdl
new file mode 100644
index 000000000..9be81044f
--- /dev/null
+++ b/testsuite/pyunit/libghdl/var.vhdl
@@ -0,0 +1,12 @@
+architecture arch of ent is
+begin
+  process
+    --  Comment for :v:
+    variable v : natural;
+  begin
+    while v < 10 loop
+      v := v + 1;
+    end loop;
+    wait;
+  end process;
+end arch;
diff --git a/testsuite/pyunit/libghdl/var_fail.vhdl b/testsuite/pyunit/libghdl/var_fail.vhdl
new file mode 100644
index 000000000..71689ff59
--- /dev/null
+++ b/testsuite/pyunit/libghdl/var_fail.vhdl
@@ -0,0 +1,12 @@
+architecture arch of ent is
+begin
+  process
+    --  Comment
+    variable v : natural;
+  begin
+    while v < 10 loop
+      v := v + 1;
+    end loop;
+    wait;
+  end process;
+end arch;