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author | Tristan Gingold <tgingold@free.fr> | 2019-09-11 06:35:56 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-09-11 06:37:29 +0200 |
commit | b91196ea76317e1f8a4725340f066fb800051040 (patch) | |
tree | e9b71de7adf8fd359d6decc2145b20ef0e259fd2 /testsuite | |
parent | 86480bfed6bce483936d585498e1498d8fde208d (diff) | |
download | ghdl-b91196ea76317e1f8a4725340f066fb800051040.tar.gz ghdl-b91196ea76317e1f8a4725340f066fb800051040.tar.bz2 ghdl-b91196ea76317e1f8a4725340f066fb800051040.zip |
testsuite/synth: add one more test in ret01
Diffstat (limited to 'testsuite')
-rw-r--r-- | testsuite/synth/ret01/ret03.vhdl (renamed from testsuite/synth/ret01/ret05.vhdl) | 6 | ||||
-rw-r--r-- | testsuite/synth/ret01/tb_ret03.vhdl | 34 | ||||
-rwxr-xr-x | testsuite/synth/ret01/testsuite.sh | 2 |
3 files changed, 38 insertions, 4 deletions
diff --git a/testsuite/synth/ret01/ret05.vhdl b/testsuite/synth/ret01/ret03.vhdl index c14e36d11..5a4cde079 100644 --- a/testsuite/synth/ret01/ret05.vhdl +++ b/testsuite/synth/ret01/ret03.vhdl @@ -1,12 +1,12 @@ library ieee; use ieee.std_logic_1164.all; -entity ret02 is +entity ret03 is port (di : std_logic_vector (7 downto 0); res : out integer); -end ret02; +end ret03; -architecture behav of ret02 is +architecture behav of ret03 is function ffs (v : std_logic_vector (7 downto 0)) return integer is begin for i in v'range loop diff --git a/testsuite/synth/ret01/tb_ret03.vhdl b/testsuite/synth/ret01/tb_ret03.vhdl new file mode 100644 index 000000000..244fdd904 --- /dev/null +++ b/testsuite/synth/ret01/tb_ret03.vhdl @@ -0,0 +1,34 @@ +entity tb_ret03 is +end tb_ret03; + +library ieee; +use ieee.std_logic_1164.all; + +architecture behav of tb_ret03 is + signal d : std_logic_vector (7 downto 0); + signal r : integer; +begin + dut: entity work.ret03 + port map (d, r); + + process + begin + d <= x"01"; + wait for 1 ns; + assert r = 0 severity failure; + + d <= x"1f"; + wait for 1 ns; + assert r = 4 severity failure; + + d <= x"e2"; + wait for 1 ns; + assert r = 7 severity failure; + + d <= x"00"; + wait for 1 ns; + assert r = -1 severity failure; + + wait; + end process; +end behav; diff --git a/testsuite/synth/ret01/testsuite.sh b/testsuite/synth/ret01/testsuite.sh index 40105e0be..94f9a09bb 100755 --- a/testsuite/synth/ret01/testsuite.sh +++ b/testsuite/synth/ret01/testsuite.sh @@ -2,7 +2,7 @@ . ../../testenv.sh -for t in ret01 ret02; do +for t in ret01 ret02 ret03; do analyze $t.vhdl tb_$t.vhdl elab_simulate tb_$t clean |