From b91196ea76317e1f8a4725340f066fb800051040 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Wed, 11 Sep 2019 06:35:56 +0200
Subject: testsuite/synth: add one more test in ret01

---
 testsuite/synth/ret01/ret03.vhdl    | 21 +++++++++++++++++++++
 testsuite/synth/ret01/ret05.vhdl    | 21 ---------------------
 testsuite/synth/ret01/tb_ret03.vhdl | 34 ++++++++++++++++++++++++++++++++++
 testsuite/synth/ret01/testsuite.sh  |  2 +-
 4 files changed, 56 insertions(+), 22 deletions(-)
 create mode 100644 testsuite/synth/ret01/ret03.vhdl
 delete mode 100644 testsuite/synth/ret01/ret05.vhdl
 create mode 100644 testsuite/synth/ret01/tb_ret03.vhdl

(limited to 'testsuite')

diff --git a/testsuite/synth/ret01/ret03.vhdl b/testsuite/synth/ret01/ret03.vhdl
new file mode 100644
index 000000000..5a4cde079
--- /dev/null
+++ b/testsuite/synth/ret01/ret03.vhdl
@@ -0,0 +1,21 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity ret03 is
+  port (di : std_logic_vector (7 downto 0);
+        res : out integer);
+end ret03;
+
+architecture behav of ret03 is
+  function ffs (v : std_logic_vector (7 downto 0)) return integer is
+  begin
+    for i in v'range loop
+      if v (i) = '1' then
+        return i;
+      end if;
+    end loop;
+    return -1;
+  end ffs;
+begin
+  res <= ffs (di);
+end behav;
diff --git a/testsuite/synth/ret01/ret05.vhdl b/testsuite/synth/ret01/ret05.vhdl
deleted file mode 100644
index c14e36d11..000000000
--- a/testsuite/synth/ret01/ret05.vhdl
+++ /dev/null
@@ -1,21 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-
-entity ret02 is
-  port (di : std_logic_vector (7 downto 0);
-        res : out integer);
-end ret02;
-
-architecture behav of ret02 is
-  function ffs (v : std_logic_vector (7 downto 0)) return integer is
-  begin
-    for i in v'range loop
-      if v (i) = '1' then
-        return i;
-      end if;
-    end loop;
-    return -1;
-  end ffs;
-begin
-  res <= ffs (di);
-end behav;
diff --git a/testsuite/synth/ret01/tb_ret03.vhdl b/testsuite/synth/ret01/tb_ret03.vhdl
new file mode 100644
index 000000000..244fdd904
--- /dev/null
+++ b/testsuite/synth/ret01/tb_ret03.vhdl
@@ -0,0 +1,34 @@
+entity tb_ret03 is
+end tb_ret03;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_ret03 is
+  signal d : std_logic_vector (7 downto 0);
+  signal r : integer;
+begin
+  dut: entity work.ret03
+    port map (d, r);
+
+  process
+  begin
+    d <= x"01";
+    wait for 1 ns;
+    assert r = 0 severity failure;
+
+    d <= x"1f";
+    wait for 1 ns;
+    assert r = 4 severity failure;
+
+    d <= x"e2";
+    wait for 1 ns;
+    assert r = 7 severity failure;
+
+    d <= x"00";
+    wait for 1 ns;
+    assert r = -1 severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/ret01/testsuite.sh b/testsuite/synth/ret01/testsuite.sh
index 40105e0be..94f9a09bb 100755
--- a/testsuite/synth/ret01/testsuite.sh
+++ b/testsuite/synth/ret01/testsuite.sh
@@ -2,7 +2,7 @@
 
 . ../../testenv.sh
 
-for t in ret01 ret02; do
+for t in ret01 ret02 ret03; do
     analyze $t.vhdl tb_$t.vhdl
     elab_simulate tb_$t
     clean
-- 
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