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| author | Tristan Gingold <tgingold@free.fr> | 2019-06-02 07:49:42 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-06-03 06:43:50 +0200 |
| commit | 6aa66fc7a9bee40e9a3d87bad712d654caad411c (patch) | |
| tree | b67ec8195f7f6ce433b6442ccb8ade69d7b49640 /testsuite | |
| parent | 85c253db43b2bf0c24e388ce2d992199c7b2893f (diff) | |
| download | ghdl-6aa66fc7a9bee40e9a3d87bad712d654caad411c.tar.gz ghdl-6aa66fc7a9bee40e9a3d87bad712d654caad411c.tar.bz2 ghdl-6aa66fc7a9bee40e9a3d87bad712d654caad411c.zip | |
sanity/004all08: add a conditional waveform.
Diffstat (limited to 'testsuite')
| -rw-r--r-- | testsuite/sanity/004all08/all08.vhdl | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/testsuite/sanity/004all08/all08.vhdl b/testsuite/sanity/004all08/all08.vhdl index d36eed366..4a47baddd 100644 --- a/testsuite/sanity/004all08/all08.vhdl +++ b/testsuite/sanity/004all08/all08.vhdl @@ -273,6 +273,7 @@ architecture behav of reg_tb is signal s1 : std_logic; signal si : integer; + signal si2 : integer; alias my_clk : std_logic is clk; @@ -307,6 +308,9 @@ begin rst_n <= '0', '1' after 25 ns; + si2 <= 1 when rst_n = '0' else + 2 when rst_n = '1'; + cmpz0 : check_zero port map (i0 => din (0)); cmpz1 : check_zero port map (i0 => din (1)); cmpz2 : check_zero port map (i0 => din (2)); |