testsuite/gna: add a test for #1684

5 files changed, 90 insertions, 0 deletions

diff --git a/testsuite/gna/issue1684/ent1.vhdl b/testsuite/gna/issue1684/ent1.vhdl
new file mode 100644
index 000000000..56a572fd8
--- /dev/null
+++ b/testsuite/gna/issue1684/ent1.vhdl
@@ -0,0 +1,16 @@
+use work.pack_RC_Add_n_F.all;
+
+entity RC_Add_n_F is
+    generic(n : natural := 4);
+    port(A, B : in bit_vector(n-1 downto 0); Cin: in bit; Sum: out bit_vector(n-1 downto 0); Cout: out bit);
+end RC_Add_n_F;
+
+architecture Arch_RC_Add_n_F of RC_Add_n_F is
+    signal result: bit_vector(n downto 0);
+begin
+    -- result <= RC_Add_n(A(3 downto 0), B, Cin);                               Works
+    -- result <= RC_Add_n(A => A(3 downto 0), B => B, Cin => Cin);              Works
+    result <= RC_Add_n(A(3 downto 0) => A(3 downto 0), B => B, Cin => Cin);     -- Throws exception when analyzing
+    Sum <= result(n-1 downto 0);
+    Cout <= result(n);
+end Arch_RC_Add_n_F;
diff --git a/testsuite/gna/issue1684/ent2.vhdl b/testsuite/gna/issue1684/ent2.vhdl
new file mode 100644
index 000000000..09b42efaa
--- /dev/null
+++ b/testsuite/gna/issue1684/ent2.vhdl
@@ -0,0 +1,17 @@
+use work.pack_RC_Add_n_F.all;
+
+entity RC_Add_n_F is
+    generic(n : natural := 4);
+    port(A, B : in bit_vector(n-1 downto 0); Cin: in bit; Sum: out bit_vector(n-1 downto 0); Cout: out bit);
+end RC_Add_n_F;
+
+architecture Arch_RC_Add_n_F of RC_Add_n_F is
+    signal result: bit_vector(n downto 0);
+begin
+    -- result <= RC_Add_n(A(3 downto 0), B, Cin);                               Works
+    -- result <= RC_Add_n(A => A(3 downto 0), B => B, Cin => Cin);              Works
+    result <= RC_Add_n(A(3 downto 1) => A(3 downto 1), a(0) => a(0), B => B, Cin => Cin);     -- Throws exception when analyzing
+ 
+    Sum <= result(n-1 downto 0);
+    Cout <= result(n);
+end Arch_RC_Add_n_F;
diff --git a/testsuite/gna/issue1684/pkg.vhdl b/testsuite/gna/issue1684/pkg.vhdl
new file mode 100644
index 000000000..0e2b87c00
--- /dev/null
+++ b/testsuite/gna/issue1684/pkg.vhdl
@@ -0,0 +1,17 @@
+package pack_RC_Add_n_F is
+    function RC_Add_n( A, B :bit_vector; Cin : bit) return bit_vector;
+end pack_RC_Add_n_F;
+    
+package body pack_RC_Add_n_F is
+    function RC_Add_n( A, B :bit_vector; Cin : bit) return bit_vector is
+        variable C:bit := Cin;
+        variable SUM:bit_vector(A'length downto 0);
+    begin
+        loop_add_m: for I in 0 to A'length-1 loop
+            SUM(I) := (A(I) xor B(I)) xor C;
+            C := (A(I) and B(I)) or (C and (A(I) xor B(I) ));
+        end loop loop_add_m;
+        SUM(A'length) := C;
+        return SUM;
+    end RC_Add_n;
+end pack_RC_Add_n_F;
diff --git a/testsuite/gna/issue1684/repro.vhdl b/testsuite/gna/issue1684/repro.vhdl
new file mode 100644
index 000000000..dc9b019c3
--- /dev/null
+++ b/testsuite/gna/issue1684/repro.vhdl
@@ -0,0 +1,30 @@
+entity repro is
+end;
+
+architecture behav of repro is
+  signal count : natural;
+
+  procedure proc (signal cnt : inout natural;
+                  signal inp : bit_vector (3 downto 0)) is
+  begin
+    report "proc executed";
+    if inp'event then
+      cnt <= cnt + 1;
+    end if;
+  end proc;
+
+  signal s : bit_vector (3 downto 0);
+begin
+  proc (count, inp (3 downto 0) => s);
+
+  process
+  begin
+    wait for 1 ns;
+    s <= x"3";
+    wait for 1 ns;
+    s <= x"b";
+    wait for 1 ns;
+    assert count = 2 severity failure;
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/gna/issue1684/testsuite.sh b/testsuite/gna/issue1684/testsuite.sh
new file mode 100755
index 000000000..9319cc259
--- /dev/null
+++ b/testsuite/gna/issue1684/testsuite.sh
@@ -0,0 +1,10 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+analyze pkg.vhdl
+analyze ent1.vhdl
+
+clean
+
+echo "Test successful"