testsuite/synth: add more tests for component

4 files changed, 136 insertions, 0 deletions

diff --git a/testsuite/synth/comp04/comp04.vhdl b/testsuite/synth/comp04/comp04.vhdl
new file mode 100644
index 000000000..af208cf44
--- /dev/null
+++ b/testsuite/synth/comp04/comp04.vhdl
@@ -0,0 +1,43 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity mand is
+  port (v : std_logic_vector (7 downto 0);
+        b : std_logic;
+        r : out std_logic_vector (7 downto 0));
+end mand;
+
+architecture behav of mand is
+begin
+  process (v, b)
+  begin
+    for i in v'range loop
+      r(i) <= v (i) and b;
+    end loop;
+  end process;
+end behav;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity comp04 is
+  port (v : std_logic_vector (7 downto 0);
+        r : out std_logic_vector (7 downto 0));
+end;
+
+architecture behav of comp04 is
+  component mand is
+    port (
+      b : std_logic;
+      v : std_logic_vector (7 downto 0);
+      r : out std_logic_vector (7 downto 0));
+  end component;
+
+begin
+  dut : mand
+    port map (v => v,
+              b => v(0),
+              r => r);
+end behav;
+
+
diff --git a/testsuite/synth/comp04/comp05.vhdl b/testsuite/synth/comp04/comp05.vhdl
new file mode 100644
index 000000000..cf36bd598
--- /dev/null
+++ b/testsuite/synth/comp04/comp05.vhdl
@@ -0,0 +1,50 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity mand is
+  port (v : std_logic_vector (7 downto 0);
+        b : out std_logic;
+        r : out std_logic_vector (7 downto 0));
+end mand;
+
+architecture behav of mand is
+begin
+  r <= not v;
+  
+  process (v)
+  begin
+    b <= '1';
+    for i in v'range loop
+      if v (i) = '0' then
+        b <= '0';
+        exit;
+      end if;
+    end loop;
+  end process;
+end behav;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity comp05 is
+  port (v : std_logic_vector (7 downto 0);
+        r : out std_logic_vector (7 downto 0));
+end;
+
+architecture behav of comp05 is
+  component mand is
+    port (
+      r : out std_logic_vector (7 downto 0);
+      b : out std_logic;  
+      v : std_logic_vector (7 downto 0));
+  end component;
+
+  signal b : std_logic;
+begin
+  dut : mand
+    port map (v => v,
+              b => b,
+              r => r);
+end behav;
+
+
diff --git a/testsuite/synth/comp04/comp06.vhdl b/testsuite/synth/comp04/comp06.vhdl
new file mode 100644
index 000000000..0d696055e
--- /dev/null
+++ b/testsuite/synth/comp04/comp06.vhdl
@@ -0,0 +1,27 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity mand is
+  port (l : std_logic_vector;
+        r : std_logic_vector := x"7c";
+        o : out std_logic_vector);
+end mand;
+
+architecture behav of mand is
+begin
+  o <= l and r;
+end behav;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity comp06 is
+  port (v : std_logic_vector (7 downto 0);
+        r : out std_logic_vector (7 downto 0));
+end;
+
+architecture behav of comp06 is
+begin
+  dut : entity work.mand
+    port map (l => v, o => r);
+end behav;
diff --git a/testsuite/synth/comp04/testsuite.sh b/testsuite/synth/comp04/testsuite.sh
new file mode 100755
index 000000000..b7974d5a7
--- /dev/null
+++ b/testsuite/synth/comp04/testsuite.sh
@@ -0,0 +1,16 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+for t in comp04 comp05 comp06; do
+#    analyze $t.vhdl tb_$t.vhdl
+#    elab_simulate tb_$t
+#    clean
+
+    synth $t.vhdl -e $t > syn_$t.vhdl
+    analyze syn_$t.vhdl #tb_$t.vhdl
+#    elab_simulate tb_$t --ieee-asserts=disable-at-0
+    clean
+done
+
+echo "Test successful"