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-rw-r--r--testsuite/synth/comp04/comp06.vhdl27
1 files changed, 27 insertions, 0 deletions
diff --git a/testsuite/synth/comp04/comp06.vhdl b/testsuite/synth/comp04/comp06.vhdl
new file mode 100644
index 000000000..0d696055e
--- /dev/null
+++ b/testsuite/synth/comp04/comp06.vhdl
@@ -0,0 +1,27 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity mand is
+ port (l : std_logic_vector;
+ r : std_logic_vector := x"7c";
+ o : out std_logic_vector);
+end mand;
+
+architecture behav of mand is
+begin
+ o <= l and r;
+end behav;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity comp06 is
+ port (v : std_logic_vector (7 downto 0);
+ r : out std_logic_vector (7 downto 0));
+end;
+
+architecture behav of comp06 is
+begin
+ dut : entity work.mand
+ port map (l => v, o => r);
+end behav;