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author | Tristan Gingold <tgingold@free.fr> | 2020-10-07 18:52:12 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2020-10-07 18:52:12 +0200 |
commit | 4a7ec846e9f18bba17d1339de4317fa76c145978 (patch) | |
tree | d65ba31b6305e2167b4d1d1c49dc06b0941f4138 /testsuite | |
parent | a9519dc6992a77e1de914aae9cb4a018f254ee27 (diff) | |
download | ghdl-4a7ec846e9f18bba17d1339de4317fa76c145978.tar.gz ghdl-4a7ec846e9f18bba17d1339de4317fa76c145978.tar.bz2 ghdl-4a7ec846e9f18bba17d1339de4317fa76c145978.zip |
testsuite/synth: add a test for previous commit.
Diffstat (limited to 'testsuite')
-rw-r--r-- | testsuite/synth/comp03/comp03.vhdl | 13 | ||||
-rw-r--r-- | testsuite/synth/comp03/comp04.vhdl | 14 | ||||
-rw-r--r-- | testsuite/synth/comp03/sub1.vhdl | 12 | ||||
-rw-r--r-- | testsuite/synth/comp03/sub2.vhdl | 14 | ||||
-rwxr-xr-x | testsuite/synth/comp03/testsuite.sh | 9 |
5 files changed, 62 insertions, 0 deletions
diff --git a/testsuite/synth/comp03/comp03.vhdl b/testsuite/synth/comp03/comp03.vhdl new file mode 100644 index 000000000..6a8a23b4d --- /dev/null +++ b/testsuite/synth/comp03/comp03.vhdl @@ -0,0 +1,13 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity comp03 is + port (p : std_logic_vector (6 downto 0); + o : out std_logic); +end comp03; + +architecture behav of comp03 is +begin + inst: entity work.sub1 + port map (p => p, o => o); +end behav; diff --git a/testsuite/synth/comp03/comp04.vhdl b/testsuite/synth/comp03/comp04.vhdl new file mode 100644 index 000000000..7663cf490 --- /dev/null +++ b/testsuite/synth/comp03/comp04.vhdl @@ -0,0 +1,14 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity comp04 is + port (p : std_logic_vector (6 downto 0); + o : out std_logic); +end comp04; + +architecture behav of comp04 is +begin + inst: entity work.sub2 + generic map (width => 8) + port map (p => p, o => o); +end behav; diff --git a/testsuite/synth/comp03/sub1.vhdl b/testsuite/synth/comp03/sub1.vhdl new file mode 100644 index 000000000..95604931c --- /dev/null +++ b/testsuite/synth/comp03/sub1.vhdl @@ -0,0 +1,12 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity sub1 is + port (p : std_logic_vector (7 downto 0); + o : out std_logic); +end sub1; + +architecture behav of sub1 is +begin + o <= p (0); +end behav; diff --git a/testsuite/synth/comp03/sub2.vhdl b/testsuite/synth/comp03/sub2.vhdl new file mode 100644 index 000000000..9b579c43a --- /dev/null +++ b/testsuite/synth/comp03/sub2.vhdl @@ -0,0 +1,14 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity sub2 is + generic + (width : natural); + port (p : std_logic_vector (width - 1 downto 0); + o : out std_logic); +end; + +architecture behav of sub2 is +begin + o <= p (0); +end behav; diff --git a/testsuite/synth/comp03/testsuite.sh b/testsuite/synth/comp03/testsuite.sh new file mode 100755 index 000000000..7272f225d --- /dev/null +++ b/testsuite/synth/comp03/testsuite.sh @@ -0,0 +1,9 @@ +#! /bin/sh + +. ../../testenv.sh + +synth_failure sub1.vhdl comp03.vhdl -e +synth_failure sub2.vhdl comp04.vhdl -e + + +echo "Test successful" |