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diff --git a/testsuite/synth/comp03/sub1.vhdl b/testsuite/synth/comp03/sub1.vhdl
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+++ b/testsuite/synth/comp03/sub1.vhdl
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+library ieee;
+use ieee.std_logic_1164.all;
+
+entity sub1 is
+ port (p : std_logic_vector (7 downto 0);
+ o : out std_logic);
+end sub1;
+
+architecture behav of sub1 is
+begin
+ o <= p (0);
+end behav;